Patents by Inventor Tsutom Takahashi

Tsutom Takahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dynamic random access memory (RAM), semiconductor storage device, and semiconductor integrated circuit (IC) device
    Patent number: 6411543
    Abstract: There is produced a first internal voltage having a difference relative to a power supply voltage, the difference being substantially equal to a threshold voltage of an address selection MOSFET of a dynamic memory cell. The first voltage is supplied to a sense amplifier as an operating voltage on a high-level side thereof. There is produced a second internal voltage having a predetermined difference relative to a circuit ground potential. The second voltage is supplied to the sense amplifier as an operating voltage on a low-level side thereof. A write signal having a high level corresponding to the first internal voltage and a low level corresponding to the second internal voltage is generated by a write amplifier to be transferred to a pair of complementary data lines connected to the dynamic memory cell. A high level, e.g., the power supply voltage representing a selection level and a low level, e.g.
    Type: Grant
    Filed: January 8, 2001
    Date of Patent: June 25, 2002
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.
    Inventors: Seiji Narui, Osamu Nagashima, Masatoshi Hasegawa, Hiroki Fujisawa, Shinichi Miyatake, Tsuyuki Suzuki, Yasunobu Aoki, Tsutom Takahashi, Kazuhiko Kajigaya
  • Dynamic random access memory (RAM), semiconductor storage device, and semiconductor integrated circuit (IC) device
    Publication number: 20010001598
    Abstract: There is produced a first internal voltage having a difference relative to a power supply voltage, the difference being substantially equal to a threshold voltage of an address selection MOSFET of a dynamic memory cell. The first voltage is supplied to a sense amplifier as an operating voltage on a high-level side thereof. There is produced a second internal voltage having a predetermined difference relative to a circuit ground potential. The second voltage is supplied to the sense amplifier as an operating voltage on a low-level side thereof. A write signal having a high level corresponding to the first internal voltage and a low level corresponding to the second internal voltage is generated by a write amplifier to be transferred to a pair of complementary data lines connected to the dynamic memory cell. A high level, e.g., the power supply voltage representing a selection level and a low level, e.g.
    Type: Application
    Filed: January 8, 2001
    Publication date: May 24, 2001
    Inventors: Seiji Narui, Osamu Nagashima, Masatoshi Hasegawa, Hiroki Fujisawa, Shinichi Miyatake, Tsuyuki Suzuki, Yasunobu Aoki, Tsutom Takahashi, Kazuhiko Kajigaya
  • Dynamic RAM, semiconductor storage device, and semiconductor integrated circuit device
    Patent number: 6201728
    Abstract: There is produced a first internal voltage having a difference relative to a power supply voltage, the difference being substantially equal to a threshold voltage of an address selection MOSFET of a dynamic memory cell. The first voltage is supplied to a sense amplifier as an operating voltage on a high-level side thereof. There is produced a second internal voltage having a predetermined difference relative to a circuit ground potential. The second voltage is supplied to the sense amplifier as an operating voltage on a low-level side thereof. A write signal having a high level corresponding to the first internal voltage and a low level corresponding to the second internal voltage is generated by a write amplifier to be transferred to a pair of complementary data lines connected to the dynamic memory cell. A high level, e.g., the power supply voltage representing a selection level and a low level, e.g.
    Type: Grant
    Filed: February 8, 1999
    Date of Patent: March 13, 2001
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.
    Inventors: Seiji Narui, Osamu Nagashima, Masatoshi Hasegawa, Hiroki Fujisawa, Shinichi Miyatake, Tsuyuki Suzuki, Yasunobu Aoki, Tsutom Takahashi, Kazuhiko Kajigaya