Abstract: A digital synchronization circuit 1000 according to the present invention includes: a polyphase clock generation circuit outputting a plurality of clock signals having the sane frequency and different phases; a selection circuit selecting and outputting one of the plurality of clock signals in accordance with the selection signal; and a selection control circuit outputting a selection signal in accordance with a clock selection signal and the plurality of clock signals. The timing at which a value of the selection signal changes from the first value to the second value is in the period in which potential levels of the clock signals respectively represented by the first and second values are the same. Thus, an output clock signal without any hazard is output which is in synchronization with an input data signal of a plurality of clock signals.