Abstract: Requestors acquire tokens before issuing access requests to a memory controller. The access requests issued are accumulated in a command queue of the memory controller. When the amount of access requests accumulated in the command queue is smaller than or equal to a first threshold, or in level 0, tokens are generated at a rate equivalent to 200% of a bus bandwidth. If the amount of accumulation is greater than the first threshold and is smaller than or equal to a second threshold, i.e., in level 1, tokens are generated at a rate equivalent to the bus bandwidth. If the amount of accumulation exceeds the second threshold, the token generation is stopped.

Abstract: Methods and apparatus provide for logically-partitioning respective processors of a multi-processing system into a plurality of resource groups; and time-allocating resources among the resource groups as a function of a predetermined algorithm.

Abstract: Methods and apparatus provide for transferring a plurality of data blocks between a shared memory and a local memory of a processor in response to a single DMA command issued by the processor to a direct memory access controller (DMAC), wherein the processor is capable of operative communication with the shared memory and the DMAC is operatively coupled to the local memory.

Abstract: An entertainment apparatus includes a storage unit that stores outside a kernel a device driver for a peripheral device. To make the peripheral device operable, a CPU causes an I/O processor to execute the device driver using a remote procedure call. Data is transferred between the peripheral device and the CPU through a direct memory access using a communication protocol that is commonly used in the apparatus.

Abstract: An entertainment apparatus includes a storage unit that stores outside a kernel a device driver for a peripheral device. To make the peripheral device operable, a CPU causes an I/O processor to execute the device driver using a remote procedure call. Data is transferred between the peripheral device and the CPU through a direct memory access using a communication protocol that is commonly used in the apparatus.

Abstract: The entertainment apparatus comprises a main bus and a subbus, which are connected to each other via a center bus having a queue. A CPU, a memory, an image processor and a DMAC are connected to the main bus. A disk drive, an I/O processor, a sound processor, and a security module are connected to the subbus. A program code, which is compressed and partially encrypted, is recorded on a secondary recording medium. The I/O processor obtains a decryption key from the security module. The I/O processor decrypts digital information read from the secondary recording medium based on the decryption key and decompresses the digital information. The decompressed digital information is written into the memory via the queue using a DMA transfer.