Patents by Inventor Tsutomu Ida

Tsutomu Ida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7453147
    Abstract: The variation of the parasitic inductance generated at the output terminal of a transistor in the final stage of a multistage amplifier unit is reduced. One side of the semiconductor chip that includes the final stage transistor is put in contact with the inner wall of a square recess formed in a wiring substrate. The semiconductor chip is positioned and fixed accurately at the bottom of the recess, whereby the drain wire of the transistor is fixed. Then, a chip edge at which the drain electrode is disposed on top of the chip is put in contact with the inner wall of the recess, which is closer to the drain bonding pad. A metallized layer is formed of the same size as that of the chip at the bottom of the recess and a fusion bonding material is supplied on the metallized layer.
    Type: Grant
    Filed: January 6, 2006
    Date of Patent: November 18, 2008
    Assignees: Renesas Technology Corp., Renesas Eastern Semiconductor, Inc.
    Inventors: Tsutomu Ida, Yoshihiko Kobayashi, Masakazu Hashizume, Yoshinori Shiokawa, Sakae Kikuchi
  • Patent number: 7223636
    Abstract: In a dividing method according to the present invention, a wiring board formed of ceramic is forced up (upper swing) by a lower clamp claw of a clamper, and some of a protruded wiring board portion protruding from a conveying chute is pressed against a support body to perform a first division under bending stress. Thereafter, the upward-located clamper is rotatably swung (lower swing) downward to allow an upper clamp claw to press down the protruded wiring board portion, thereby performing a reverse division at the first division section again as a second division. Since the second division allows a tensile force to act on a remaining and thin non-divided resin portion, the non-divided resin portion is torn off. Thus, the perfect division is enabled. Fractionalizing is done by a one-row division and an individual division so that each semiconductor device is formed.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: May 29, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Yoshihiko Kobayashi, Susumu Sato, Koki Tanimoto, Tomio Yamada, Hirokazu Nakajima, Tomoaki Kudaishi, Yoshinori Shiokawa, Toshiharu Niitsu, Tsutomu Ida
  • Publication number: 20070105283
    Abstract: In a dividing method according to the present invention, a wiring board formed of ceramic is forced up (upper swing) by a lower clamp claw of a clamper, and some of a protruded wiring board portion protruding from a conveying chute is pressed against a support body to perform a first division under bending stress. Thereafter, the upward-located clamper is rotatably swung (lower swing) downward to allow an upper clamp claw to press down the protruded wiring board portion, thereby performing a reverse division at the first division section again as a second division. Since the second division allows a tensile force to act on a remaining and thin non-divided resin portion, the non-divided resin portion is torn off. Thus, the perfect division is enabled. Fractionalizing is done by a one-row division and an individual division so that each semiconductor device is formed.
    Type: Application
    Filed: December 29, 2006
    Publication date: May 10, 2007
    Inventors: Yoshihiko Kobayashi, Susumu Sato, Koki Tanimoto, Tomio Yamada, Hirokazu Nakajima, Tomoaki Kudaishi, Yoshinori Shiokawa, Toshiharu Niitsu, Tsutomu Ida
  • Patent number: 7119004
    Abstract: The variation of the parasitic inductance generated at the output terminal of a transistor in the final stage of a multistage amplifier unit is reduced. One side of the semiconductor chip that includes the final stage transistor is put in contact with the inner wall of a square recess formed in a wiring substrate. The semiconductor chip is positioned and fixed accurately at the bottom of the recess, whereby the drain wire of the transistor is fixed. Then, a chip edge at which the drain electrode is disposed on top of the chip is put in contact with the inner wall of the recess, which is closer to the drain bonding pad. A metallized layer is formed of the same size as that of the chip at the bottom of the recess and a fusion bonding material is supplied on the metallized layer.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: October 10, 2006
    Assignees: Renesas Technology Corp., Renesas Eastern Japan semiconductor, Inc.
    Inventors: Tsutomu Ida, Yoshihiko Kobayashi, Masakazu Hashizume, Yoshinori Shiokawa, Sakae Kikuchi
  • Publication number: 20060118970
    Abstract: The variation of the parasitic inductance generated at the output terminal of a transistor in the final stage of a multistage amplifier unit is reduced. One side of the semiconductor chip that includes the final stage transistor is put in contact with the inner wall of a square recess formed in a wiring substrate. The semiconductor chip is positioned and fixed accurately at the bottom of the recess, whereby the drain wire of the transistor is fixed. Then, a chip edge at which the drain electrode is disposed on top of the chip is put in contact with the inner wall of the recess, which is closer to the drain bonding pad. A metallized layer is formed of the same size as that of the chip at the bottom of the recess and a fusion bonding material is supplied on the metallized layer.
    Type: Application
    Filed: January 6, 2006
    Publication date: June 8, 2006
    Inventors: Tsutomu Ida, Yoshihiko Kobayashi, Masakazu Hashizume, Yoshinori Shiokawa, Sakae Kikuchi
  • Patent number: 6989587
    Abstract: There is provided a semiconductor device with enhanced reliability having a heat sink mounting a plurality of semiconductor chips, a plurality of inner leads connected electrically to the semiconductor chips, a molding body for resin molding the plurality of semiconductor chips and the plurality of inner leads, a plurality of wires for providing electrical connections between the respective electrodes of the semiconductor chips and the inner leads corresponding thereto, and wide outer leads connecting to the inner leads and exposed outside the molding body. A plurality of slits are formed in the respective portions of the outer leads located outside the molding body to extend lengthwise in directions in which the outer leads are extracted. This achieves a reduction in lead stress which is placed on the outer leads by thermal stress or the like after the mounting of a MOSFET and thereby enhances the reliability of the MOSFET.
    Type: Grant
    Filed: December 9, 2003
    Date of Patent: January 24, 2006
    Assignees: Renesas Technology Corp., Renesas Esatern Japan Semiconductor, Inc.
    Inventors: Mamoru Ito, Akira Muto, Tomio Yamada, Tsuneo Endoh, Satoru Konishi, Kazuaki Uehara, Tsutomu Ida, Koji Odaira, Hirokazu Nakajima
  • Publication number: 20050250254
    Abstract: A method of manufacturing a semiconductor device able to reduce the number of manufacturing steps and attain the rationalization of a manufacturing line is disclosed. The semiconductor device is a high-frequency module assembled by mounting chip parts (22) and semiconductor pellets (21) onto each of wiring substrates (2) formed on a matrix substrate (27) after inspection. A defect mark (2e) is affixed to a wiring substrate (2) as a block judged to be defective in the inspection of the matrix substrate (27), then in a series of subsequent assembling steps the defect mark (e) is recognized and the assembling work for the wiring substrate (2) with the defect mark (2e) thereon is omitted to attain the rationalization of a manufacturing line.
    Type: Application
    Filed: July 12, 2005
    Publication date: November 10, 2005
    Inventors: Akio Ishizu, Kazutoshi Takashima, Shiro Oba, Yoshihiko Kobayashi, Tsutomu Ida, Shigeru Haga, Susumu Takada, Iwamichi Koujiro, Norinaga Arai, Yuji Kakegawa
  • Patent number: 6946306
    Abstract: A method of manufacturing a semiconductor device able to reduce the number of manufacturing steps and attain the rationalization of a manufacturing line is disclosed. The semiconductor device is a high-frequency module assembled by mounting chip parts (22) and semiconductor pellets (21) onto each of wiring substrates (2) formed on a matrix substrate (27) after inspection. A defect mark (2e) is affixed to a wiring substrate (2) as a block judged to be defective in the inspection of the matrix substrate (27), then in a series of subsequent assembling steps the defect mark (e) is recognized and the assembling work for the wiring substrate (2) with the defect mark (2e) thereon is omitted to attain the rationalization of a manufacturing line.
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: September 20, 2005
    Assignees: Renesas Technology Corp., Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Akio Ishizu, Kazutoshi Takashima, Shiro Oba, Yoshihiko Kobayashi, Tsutomu Ida, Shigeru Haga, Susumu Takada, Iwamichi Koujiro, Norinaga Arai, Yuji Kakegawa
  • Publication number: 20050101052
    Abstract: In a dividing method according to the present invention, a wiring board formed of ceramic is forced up (upper swing) by a lower clamp claw of a clamper, and some of a protruded wiring board portion protruding from a conveying chute is pressed against a support body to perform a first division under bending stress. Thereafter, the upward-located clamper is rotatably swung (lower swing) downward to allow an upper clamp claw to press down the protruded wiring board portion, thereby performing a reverse division at the first division section again as a second division. Since the second division allows a tensile force to act on a remaining and thin non-divided resin portion, the non-divided resin portion is torn off. Thus, the perfect division is enabled. Fractionalizing is done by a one-row division and an individual division so that each semiconductor device is formed.
    Type: Application
    Filed: October 12, 2004
    Publication date: May 12, 2005
    Inventors: Yoshihiko Kobayashi, Susumu Sato, Koki Tanimoto, Tomio Yamada, Hirokazu Nakajima, Tomoaki Kudaishi, Yoshinori Shiokawa, Toshiharu Niitsu, Tsutomu Ida
  • Publication number: 20050064612
    Abstract: A method of manufacturing a semiconductor device able to reduce the number of manufacturing steps and attain the rationalization of a manufacturing line is disclosed. The semiconductor device is a high-frequency module assembled by mounting chip parts (22) and semiconductor pellets (21) onto each of wiring substrates (2) formed on a matrix substrate (27) after inspection. A defect mark (2e) is affixed to a wiring substrate (2) as a block judged to be defective in the inspection of the matrix substrate (27), then in a series of subsequent assembling steps the defect mark (e) is recognized and the assembling work for the wiring substrate (2) with the defect mark (2e) thereon is omitted to attain the rationalization of a manufacturing line.
    Type: Application
    Filed: November 9, 2004
    Publication date: March 24, 2005
    Inventors: Akio Ishizu, Kazutoshi Takashima, Shiro Oba, Yoshihiko Kobayashi, Tsutomu Ida, Shigeru Haga, Susumu Takada, Iwamichi Koujiro, Norinaga Arai, Yuji Kakegawa
  • Patent number: 6852553
    Abstract: A method of manufacturing a semiconductor device able to reduce the number of manufacturing steps and attain the rationalization of a manufacturing line is disclosed. The semiconductor device is a high-frequency module assembled by mounting chip parts (22) and semiconductor pellets (21) onto each of wiring substrates (2) formed on a matrix substrate (27) after inspection. A defect mark (2e) is affixed to a wiring substrate (2) as a block judged to be defective in the inspection of the matrix substrate (27), then in a series of subsequent assembling steps the defect mark (e) is recognized and the assembling work for the wiring substrate (2) with the defect mark (2e) thereon is omitted to attain the rationalization of a manufacturing line.
    Type: Grant
    Filed: February 15, 2001
    Date of Patent: February 8, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Akio Ishizu, Kazutoshi Takashima, Shiro Oba, Yoshihiko Kobayashi, Tsutomu Ida, Shigeru Haga, Susumu Takada, Iwamichi Koujiro, Norinaga Arai, Yuji Kakegawa
  • Publication number: 20040245655
    Abstract: The variation of the parasitic inductance generated at the output terminal of a transistor in the final stage of a multistage amplifier unit is reduced. One side of the semiconductor chip that includes the final stage transistor is put in contact with the inner wall of a square recess formed in a wiring substrate. The semiconductor chip is positioned and fixed accurately at the bottom of the recess, whereby the drain wire of the transistor is fixed. Then, a chip edge at which the drain electrode is disposed on top of the chip is put in contact with the inner wall of the recess, which is closer to the drain bonding pad. A metallized layer is formed of the same size as that of the chip at the bottom of the recess and a fusion bonding material is supplied on the metallized layer.
    Type: Application
    Filed: February 13, 2004
    Publication date: December 9, 2004
    Inventors: Tsutomu Ida, Yoshihiko Kobayashi, Masakazu Hashizume, Yoshinori Shiokawa, Sakae Kikuchi
  • Publication number: 20040113248
    Abstract: There is provided a semiconductor device with enhanced reliability having a heat sink mounting a plurality of semiconductor chips, a plurality of inner leads connected electrically to the semiconductor chips, a molding body for resin molding the plurality of semiconductor chips and the plurality of inner leads, a plurality of wires for providing electrical connections between the respective electrodes of the semiconductor chips and the inner leads corresponding thereto, and wide outer leads connecting to the inner leads and exposed outside the molding body. A plurality of slits are formed in the respective portions of the outer leads located outside the molding body to extend lengthwise in directions in which the outer leads are extracted. This achieves a reduction in lead stress which is placed on the outer leads by thermal stress or the like after the mounting of a MOSFET and thereby enhances the reliability of the MOSFET.
    Type: Application
    Filed: December 9, 2003
    Publication date: June 17, 2004
    Inventors: Mamoru Ito, Akira Muto, Tomio Yamada, Tsuneo Endoh, Satoru Konishi, Kazuaki Uehara, Tsutomu Ida, Koji Odaira, Hirokazu Nakajima
  • Patent number: 6709890
    Abstract: In a method of manufacturing a high frequency module to be assembled by providing, on a wiring board, a chip part and a semiconductor pellet to be bare chip mounted and then mounting the chip part and the semiconductor pellet through soldering, the wiring board is separated from a heat block with the semiconductor pellet pressurized against the wiring board in a main heating portion heating and melting a reflow solder, thereby cooling a soldering portion. Consequently, the generation of a void in the soldering portion can be prevented and the connecting reliability of the soldering portion can be enhanced. In addition, a degree of mounting horizontality of the semiconductor pellet on the wiring board can be enhanced.
    Type: Grant
    Filed: February 15, 2001
    Date of Patent: March 23, 2004
    Assignees: Renesas Technology Corporation, Hitachi Tobu Semiconductor Ltd.
    Inventors: Tsutomu Ida, Akio Ishizu, Masakazu Hashizume, Isao Hagiwara, Yoshinori Shiokawa
  • Publication number: 20030003622
    Abstract: A method of manufacturing a semiconductor device able to reduce the number of manufacturing steps and attain the rationalization of a manufacturing line is disclosed. The semiconductor device is a high-frequency module assembled by mounting chip parts (22) and semiconductor pellets (21) onto each of wiring substrates (2) formed on a matrix substrate (27) after inspection. A defect mark (2e) is affixed to a wiring substrate (2) as a block judged to be defective in the inspection of the matrix substrate (27), then in a series of subsequent assembling steps the defect mark (e) is recognized and the assembling work for the wiring substrate (2) with the defect mark (2e) thereon is omitted to attain the rationalization of a manufacturing line.
    Type: Application
    Filed: May 3, 2002
    Publication date: January 2, 2003
    Inventors: Akio Ishizu, Kazutoshi Takashima, Shiro Oba, Yoshihiko Kobayashi, Tsutomu Ida, Shigeru Haga, Susumu Takada, Iwamichi Koujiro, Norinaga Arai, Yuji Kakegawa
  • Publication number: 20010014490
    Abstract: In a method of manufacturing a high frequency module to be assembled by providing, on a wiring board, a chip part and a semiconductor pellet to be bare chip mounted and then mounting the chip part and the semiconductor pellet through soldering, the wiring board is separated from a heat block with the semiconductor pellet pressurized against the wiring board in a main heating portion heating and melting a reflow solder, thereby cooling a soldering portion. Consequently, the generation of a void in the soldering portion can be prevented and the connecting reliability of the soldering portion can be enhanced. In addition, a degree of mounting horizontality of the semiconductor pellet on the wiring board can be enhanced.
    Type: Application
    Filed: February 15, 2001
    Publication date: August 16, 2001
    Inventors: Tsutomu Ida, Akio Ishizu, Masakazu Hashizume, Isao Hagiwara, Yoshinori Shiokawa
  • Patent number: 5844484
    Abstract: The present invention relates to a theft preventive apparatus used as attached to a commodity or the like exhibited in a shop, for outputting an alarm when detached therefrom.Conventionally, an alarm output device for outputting alarm information comprises a speaker for giving an alarm sound. However, it is impossible, where a plurality of theft prevention apparatus are arranged close to one another, to determine instantly which theft prevention apparatus is giving the alarm sound. The theft preventive apparatus of this invention comprises a box (2) attachable to an object of theft prevention (E) and including detecting means (P) for detecting a preliminary stealing act, and alarm output means (Q) for outputting alarm information based on detection information from the detecting means (P), said box (2) housing light emitting means (20) for emitting light based on the detection information from the detecting means (P) outwardly of said box (2).
    Type: Grant
    Filed: April 28, 1995
    Date of Patent: December 1, 1998
    Assignee: Kubota Corporation
    Inventors: Hiroyuki Fujiuchi, Masaaki Takeshita, Keinji Uchida, Tsutomu Ida, Mitsuhiko Nakajima
  • Patent number: 5656998
    Abstract: The present invention relates to a detector for theft prevention used in contact with a commodity or the like exhibited in a shop.Conventionally, an operated portion for contacting a commodity or the like is pivotable only in one direction from a projected position. The commodity or the like cannot be moved in directions requiring the operated portion to pivot in directions other than that direction. A forcible movement would damage the operated portion.In a detector for theft prevention of this invention, a switch (3) provided for a box (2) thereof has a pivotable operated portion (3a) biased to return to a position projecting from a surface (2c, 2d) contacting an object of theft prevention (E). The operated portion (3a) is pivotable in a plurality of directions including at least two opposite directions (e1, e2). The detector for theft prevention is properly operable for movements in varied directions of the object of theft prevention (E).
    Type: Grant
    Filed: April 26, 1995
    Date of Patent: August 12, 1997
    Assignee: Kubota Corporation
    Inventors: Hiroyuki Fujiuchi, Masaaki Takeshita, Kenji Uchida, Tsutomu Ida, Hisakazu Okumura, Mitsuhiko Nakajima
  • Patent number: 5610587
    Abstract: A theft preventive apparatus is attached to a commodity or the like exhibited in a shop, for outputting an alarm when detached therefrom.Conventionally, a battery is used as a power source for driving an alarm output device, and power supply is turned on and off by moving the battery. Even in a non-use state, an operation could be started inadvertently by vibration or the like.
    Type: Grant
    Filed: April 27, 1995
    Date of Patent: March 11, 1997
    Assignee: Kubota Corporation
    Inventors: Hiroyuki Fujiuchi, Masaaki Takeshita, Kenji Uchida, Tsutomu Ida, Hisakazu Okumura, Mitsuhiko Nakajima