Patents by Inventor Tsutomu Ishiba

Tsutomu Ishiba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6815741
    Abstract: By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements in the wafer. The difference between the maximum value and minimum value of the lattice distortions of a III-V single crystal at a normal temperature is set to at most 4×10−5, and the density of Si atoms contained in the III-V single crystal is set to at most 1×1016 cm−3, whereby the characteristics of semiconductor elements whose parent material is the III-V single crystal can be made uniform.
    Type: Grant
    Filed: July 23, 2003
    Date of Patent: November 9, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Yoshihisa Fujisaki, Yukio Takano, Tsutomu Ishiba
  • Publication number: 20040124447
    Abstract: By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements in the wafer. The difference between the maximum value and minimum value of the lattice distortions of a III-V single crystal at a normal temperature is set to at most 4×10−5, and the density of Si atoms contained in the III-V single crystal is set to at most 1×1016 cm−3, whereby the characteristics of semiconductor elements whose parent material is the III-V single crystal can be made uniform.
    Type: Application
    Filed: July 23, 2003
    Publication date: July 1, 2004
    Inventors: Yoshihisa Fujisaki, Yukio Takano, Tsutomu Ishiba
  • Patent number: 6630697
    Abstract: By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer si reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements in the wafer. The difference between the maximum value and minimum value of the lattice distortions of a GaAs single crystal at a normal temperature is set to at most 4×10−5, and the density of Si atoms contained in the GaAs single crystal is set to at most 1×1016 cm−3, whereby the characteristics of semiconductor elements whose parent material is the GaAs single crystal can be made uniform.
    Type: Grant
    Filed: July 25, 2001
    Date of Patent: October 7, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihisa Fujisaki, Yukio Takano, Tsutomu Ishiba
  • Publication number: 20010045621
    Abstract: By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer si reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements in the wafer. The difference between the maximum value and minimum value of the lattice distortions of a GaAs single crystal at a normal temperature is set to at most 4×10−5, and the density of Si atoms contained in the GaAs single crystal is set to at most 1×1016 cm−3, whereby the characteristics of semiconductor elements whose parent material is the GaAs single crystal can be made uniform.
    Type: Application
    Filed: July 25, 2001
    Publication date: November 29, 2001
    Inventors: Yoshihisa Fujisaki, Yukio Takano, Tsutomu Ishiba
  • Patent number: 6297523
    Abstract: By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements in the wafer. The difference between the maximum value and minimum value of the lattice distortions of a GaAs single crystal at a normal temperature is set to at most 4×10−5 and the density of Si atoms contained in the GaAs single crystal is set to at most 1×1016 cm−3, whereby the characteristics of semiconductor elements whose parent material is the GaAs single crystal can be made uniform.
    Type: Grant
    Filed: August 18, 1993
    Date of Patent: October 2, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihisa Fujisaki, Yukio Takano, Tsutomu Ishiba
  • Patent number: 6294804
    Abstract: By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements inthe wafer. The difference between the maximum value and minimum value of the lattice distortions of a GaAs single crystal at a normal temperature is set to at most 4×10−5, and the density of Si atoms contained in the GaAs single crystal is set to at most 1×1016 cm−3, whereby the characteristics of semiconductor elements whose parent matrial is the GaAs single crystal can be made uniform.
    Type: Grant
    Filed: October 3, 1997
    Date of Patent: September 25, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihisa Fujisaki, Yukio Takano, Tsutomu Ishiba
  • Patent number: 5770873
    Abstract: By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements in the wafer. The difference between the maximum value and the minimum value of the lattice distortions of a GaAs single crystal at a normal temperature is set to at most 4.times.10.sup.-5, and the density of Si atoms contained in the GaAs single crystal is set to at most 1.times.10.sup.16 cm.sup.-3, whereby the characteristics of semiconductor elements whose parent material (substrate) is the GaAs single crystal can be made uniform.
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: June 23, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihisa Fujisaki, Yukio Takano, Tsutomu Ishiba
  • Patent number: 5733805
    Abstract: By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements inthe wafer. The difference between the maximum value and minimum value of the lattice distortions of a GaAs single crystal at a normal temperature is set to at most 4.times.10.sup.-5, and the density of Si atoms contained in the GaAs single crystal is set to at most 1.times.10.sup.16 cm.sup.-3, whereby the characteristics of semiconductor elements whose parent matrial is the GaAs single crystal can be made uniform.
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: March 31, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihisa Fujisaki, Yukio Takano, Tsutomu Ishiba