Patents by Inventor Tsutomu Kobori

Tsutomu Kobori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11239187
    Abstract: A ground pad is disposed on a substrate. A plurality of transistors, each grounded at an emitter thereof, are in a first direction on a surface of the substrate. An input line connected to bases of the transistors is on the substrate. At least two shunt inductors are each connected at one end thereof to the input line and connected at the other end thereof to the ground pad. In the first direction, the two shunt inductors are on opposite sides of a center of a region where the transistors are arranged.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: February 1, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Tsutomu Kobori, Hiroshi Okabe, Shigeru Yoshida, Shingo Yanagihara, Yoshifumi Takahashi
  • Publication number: 20210344312
    Abstract: A power amplifier device includes a semiconductor substrate; a plurality of first transistors that are provided on the semiconductor substrate and receive input of a radio-frequency signal; a plurality of second transistors that are provided on the semiconductor substrate and electrically connected to the respective plurality of first transistors, and output a radio-frequency output signal obtained by amplifying the radio-frequency signal; a plurality of first bumps provided so as to overlay the respective plurality of first transistors; and a second bump provided away from the plurality of first bumps and provided so as not to overlay the plurality of first transistors and the plurality of second transistors. When viewed in plan from a direction perpendicular to a surface of the semiconductor substrate, a first transistor and a first bump, a second transistor, the second bump, a second transistor, and a first transistor and a first bump are arranged in sequence.
    Type: Application
    Filed: April 28, 2021
    Publication date: November 4, 2021
    Inventors: Tsutomu KOBORI, Shingo YANAGIHARA, Yoshifumi TAKAHASHI, Hiroshi OKABE
  • Publication number: 20210013164
    Abstract: A ground pad is disposed on a substrate. A plurality of transistors, each grounded at an emitter thereof, are in a first direction on a surface of the substrate. An input line connected to bases of the transistors is on the substrate. At least two shunt inductors are each connected at one end thereof to the input line and connected at the other end thereof to the ground pad. In the first direction, the two shunt inductors are on opposite sides of a center of a region where the transistors are arranged.
    Type: Application
    Filed: July 9, 2020
    Publication date: January 14, 2021
    Inventors: Tsutomu KOBORI, Hiroshi OKABE, Shigeru YOSHIDA, Shingo YANAGIHARA, Yoshifumi TAKAHASHI
  • Patent number: 9263559
    Abstract: A radio communication device includes a power amplifier having a semiconductor device formed with a plurality of unit transistors. Base electrodes of the unit transistors are connected with each other by a base line, and an input capacitor is connected to the base line such that the input capacitor is commonly and electrically connected to the base electrodes of a plurality of the unit transistors.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: February 16, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Satoshi Sasaki, Yasunari Umemoto, Yasuo Osone, Tsutomu Kobori, Chushiro Kusano, Isao Ohbu, Kenji Sasaki
  • Patent number: 9014654
    Abstract: A semiconductor apparatus includes multiple field effect transistors provided between an antenna terminal to be connected to an antenna and multiple external terminals through which RF signals are capable of being supplied and a voltage generating circuit. When the field effect transistors provided between one of the multiple external terminals and the antenna terminal are turned off, the voltage generating unit charges a capacitor via a resistor circuit by switching the polarity of the RF signal to be supplied to the other external terminal with respect to the control signal and outputs a voltage based on a sum of the charge voltage and the voltage of the control signal as the gate drive voltage. The resistor circuit includes a first resistor including positive temperature characteristics and a second resistor including negative temperature characteristics.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: April 21, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Tsutomu Kobori, Shigeki Koya, Akishige Nakajima, Yasushi Shigeno
  • Publication number: 20140361406
    Abstract: A radio communication device includes a power amplifier having a semiconductor device formed with a plurality of unit transistors. Base electrodes of the unit transistors are connected with each other by a base line, and an input capacitor is connected to the base line such that the input capacitor is commonly and electrically connected to the base electrodes of a plurality of the unit transistors.
    Type: Application
    Filed: August 27, 2014
    Publication date: December 11, 2014
    Inventors: Satoshi SASAKI, Yasunari UMEMOTO, Yasuo OSONE, Tsutomu KOBORI, Chushiro KUSANO, Isao OHBU, Kenji SASAKI
  • Patent number: 8860093
    Abstract: A technology which allows a reduction in the thermal resistance of a semiconductor device used in a radio communication device, and the miniaturization thereof is provided. For example, the semiconductor device can include a plurality of unit transistors Q, transistor formation regions 3a, 3b, and 3e each having a first number (e.g., seven) of the unit transistors Q, and transistor formation regions 3c and 3d each having a second number (e.g., four) of the unit transistors Q. The transistor formation regions 3c and 3d are located between the transistor formation regions 3a, 3b, 3e, and 3f, and the first number is larger than the second number.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: October 14, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Satoshi Sasaki, Yasunari Umemoto, Yasuo Osone, Tsutomu Kobori, Chushiro Kusano, Isao Ohbu, Kenji Sasaki
  • Publication number: 20140043110
    Abstract: A semiconductor apparatus includes multiple field effect transistors provided between an antenna terminal to be connected to an antenna and multiple external terminals through which RF signals are capable of being supplied and a voltage generating circuit. When the field effect transistors provided between one of the multiple external terminals and the antenna terminal are turned off, the voltage generating unit charges a capacitor via a resistor circuit by switching the polarity of the RF signal to be supplied to the other external terminal with respect to the control signal and outputs a voltage based on a sum of the charge voltage and the voltage of the control signal as the gate drive voltage. The resistor circuit includes a first resistor including positive temperature characteristics and a second resistor including negative temperature characteristics.
    Type: Application
    Filed: October 16, 2013
    Publication date: February 13, 2014
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Tsutomu KOBORI, Shigeki KOYA, Akishige NAKAJIMA, Yasushi SHIGENO
  • Patent number: 8546939
    Abstract: A technology is provided so that RF modules used for cellular phones etc. can be reduced in size. Over a wiring board constituting an RF module, there are provided a first semiconductor chip in which an amplifier circuit is formed and a second semiconductor chip in which a control circuit for controlling the amplifier circuit is formed. A bonding pad over the second semiconductor chip is connected with a bonding pad over the first semiconductor chip directly by a wire without using a relay pad. In this regard, the bonding pad formed over the first semiconductor chip is not square but rectangular (oblong).
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: October 1, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kenji Sasaki, Tomonori Tanoue, Sakae Kikuchi, Toshifumi Makino, Takeshi Sato, Tsutomu Kobori, Yasunari Umemoto, Takashi Kitahara
  • Publication number: 20120261799
    Abstract: A technology which allows a reduction in the thermal resistance of a semiconductor device used in a radio communication device, and the miniaturization thereof is provided. For example, the semiconductor device can include a plurality of unit transistors Q, transistor formation regions 3a, 3b, and 3e each having a first number (e.g., seven) of the unit transistors Q, and transistor formation regions 3c and 3d each having a second number (e.g., four) of the unit transistors Q. The transistor formation regions 3c and 3d are located between the transistor formation regions 3a, 3b, 3e, and 3f, and the first number is larger than the second number.
    Type: Application
    Filed: June 29, 2012
    Publication date: October 18, 2012
    Inventors: Satoshi SASAKI, Yasunari UMEMOTO, Yasuo OSONE, Tsutomu KOBORI, Chushiro KUSANO, Isao OHBU, Kenji SASAKI
  • Patent number: 8227836
    Abstract: A technology which allows a reduction in the thermal resistance of a semiconductor device and the miniaturization thereof is provided. The semiconductor device has a plurality of unit transistors Q, transistor formation regions 3a, 3b, and 3e each having a first number (e.g., seven) of the unit transistors Q, and transistor formation regions 3c and 3d each having a second number (e.g., four) of the unit transistors Q. The transistor formation regions 3c and 3d are located between the transistor formation regions 3a, 3b, 3e, and 3f, and the first number is larger than the second number.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: July 24, 2012
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Satoshi Sasaki, Yasunari Umemoto, Yasuo Osone, Tsutomu Kobori, Chushiro Kusano, Isao Ohbu, Kenji Sasaki
  • Patent number: 8115234
    Abstract: There is provided a technique for reducing the occurrence of higher harmonics which occur from a field effect transistor, particularly a field effect transistor configuring a switching element of an antenna switch. In a transistor having a meander structure, the gate width of a partial transistor closest to a gate input side is increased. More specifically, a comb-like electrode is made longer than the other comb-like electrodes. In other words, a finger length is made greater than any other finger length. In particular, the comb-like electrode has the greatest length in all the comb-like electrodes.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: February 14, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Akishige Nakajima, Yasushi Shigeno, Hitoshi Akamine, Tsutomu Kobori, Izumi Arai, Kazuto Tajima, Tomoyuki Ishikawa, Jyun Funaki
  • Publication number: 20100096667
    Abstract: There is provided a technique for reducing the occurrence of higher harmonics which occur from a field effect transistor, particularly a field effect transistor configuring a switching element of an antenna switch. In a transistor having a meander structure, the gate width of a partial transistor closest to a gate input side is increased. More specifically, a comb-like electrode is made longer than the other comb-like electrodes. In other words, a finger length is made greater than any other finger length. In particular, the comb-like electrode has the greatest length in all the comb-like electrodes.
    Type: Application
    Filed: September 23, 2009
    Publication date: April 22, 2010
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Akishige NAKAJIMA, Yasushi SHIGENO, Hitoshi AKAMINE, Tsutomu KOBORI, Izumi ARAI, Kazuto TAJIMA, Tomoyuki ISHIKAWA, Jyun FUNAKI
  • Publication number: 20100032720
    Abstract: A technology which allows a reduction in the thermal resistance of a semiconductor device and the miniaturization thereof is provided. The semiconductor device has a plurality of unit transistors Q, transistor formation regions 3a, 3b, and 3e each having a first number (e.g., seven) of the unit transistors Q, and transistor formation regions 3c and 3d each having a second number (e.g., four) of the unit transistors Q. The transistor formation regions 3c and 3d are located between the transistor formation regions 3a, 3b, 3e, and 3f, and the first number is larger than the second number.
    Type: Application
    Filed: October 15, 2009
    Publication date: February 11, 2010
    Inventors: Satoshi SASAKI, Yasunari Umemoto, Yasuo Osone, Tsutomu Kobori, Chushiro Kusano, Isao Ohbu, Kenji Sasaki
  • Patent number: 7622756
    Abstract: A technology which allows a reduction in the thermal resistance of a semiconductor device and the miniaturization thereof is provided. The semiconductor device has a plurality of unit transistors Q, transistor formation regions 3a, 3b, and 3e each having a first number (seven) of the unit transistors Q, and transistor formation regions 3c and 3d each having a second number (four) of the unit transistors Q. The transistor formation regions 3c and 3d are located between the transistor formation regions 3a, 3b, 3e, and 3f and the first number is larger than the second number.
    Type: Grant
    Filed: December 28, 2005
    Date of Patent: November 24, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Satoshi Sasaki, Yasunari Umemoto, Yasuo Osone, Tsutomu Kobori, Chushiro Kusano, Isao Ohbu, Kenji Sasaki
  • Publication number: 20070190962
    Abstract: A technology is provided so that RF modules used for cellular phones etc. can be reduced in size. Over a wiring board constituting an RF module, there are provided a first semiconductor chip in which an amplifier circuit is formed and a second semiconductor chip in which a control circuit for controlling the amplifier circuit is formed. A bonding pad over the second semiconductor chip is connected with a bonding pad over the first semiconductor chip directly by a wire without using a relay pad. In this regard, the bonding pad formed over the first semiconductor chip is not square but rectangular (oblong).
    Type: Application
    Filed: December 29, 2006
    Publication date: August 16, 2007
    Inventors: Kenji Sasaki, Tomonori Tanoue, Sakae Kikuchi, Toshifumi Makino, Takeshi Sato, Tsutomu Kobori, Yasunari Umemoto, Takashi Kitahara
  • Publication number: 20060138460
    Abstract: A technology which allows a reduction in the thermal resistance of a semiconductor device and the miniaturization thereof is provided. The semiconductor device has a plurality of unit transistors Q, transistor formation regions 3a, 3b, and 3e each having a first number (seven) of the unit transistors Q, and transistor formation regions 3c and 3d each having a second number (four) of the unit transistors Q. The transistor formation regions 3c and 3d are located between the transistor formation regions 3a, 3b, 3e, and 3f and the first number is larger than the second number.
    Type: Application
    Filed: December 28, 2005
    Publication date: June 29, 2006
    Inventors: Satoshi Sasaki, Yasunari Umemoto, Yasuo Osone, Tsutomu Kobori, Chushiro Kusano, Isao Ohbu, Kenji Sasaki
  • Publication number: 20020024392
    Abstract: Disclosed herein is a high frequency power amplifier system having a transistor comprised of a first electrode, a second electrode and a control electrode and for controlling current which flows between the first electrode and the second electrode by applying a potential to the control electrode, and a resistance type potential divider circuit for determining a dc bias potential applied to the control electrode of the transistor, and wherein an input signal is inputted to the control electrode, an output signal is outputted from the first electrode and a control signal is inputted to the resistance type potential divider circuit. One resistor of the resistance type potential divider circuit is comprised of a temperature compensating resistor whose resistance value varies linearly, so that a temperature characteristic of an idle current defined as an output when the control signal is not inputted, assumes a negative temperature characteristic.
    Type: Application
    Filed: October 25, 2001
    Publication date: February 28, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Masashi Maruyama, Hitoshi Akamine, Tsutomu Kobori, Shinji Moriyama
  • Patent number: 6329879
    Abstract: Disclosed herein is a high frequency power amplifier system having a transistor comprised of a first electrode, a second electrode and a control electrode and for controlling current which flows between the first electrode and the second electrode by applying a potential to the control electrode, and a resistance type potential divider circuit for determining a dc bias potential applied to the control electrode of the transistor, and wherein an input signal is inputted to the control electrode, an output signal is outputted from the first electrode and a control signal is inputted to the resistance type potential divider circuit. One resistor of the resistance type potential divider circuit is comprised of a temperature compensating resistor whose resistance value varies linearly, so that a temperature characteristic of an idle current defined as an output when the control signal is not inputted, assumes a negative temperature characteristic.
    Type: Grant
    Filed: November 10, 1999
    Date of Patent: December 11, 2001
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd., Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Masashi Maruyama, Hitoshi Akamine, Tsutomu Kobori, Shinji Moriyama