Patents by Inventor Tsutomu Koga
Tsutomu Koga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10579304Abstract: Provided is a storage apparatus including a plurality of storage devices which store data, a controller which executes data input/output processing to the storage devices, and a processor which transmits/receives information with the controller, wherein the controller manages a plurality of different tag numbers by separating the tag numbers into a plurality of groups, and upon receiving a first command from the processor, assigns a tag number belonging to one group among the plurality of groups to the first command, and transfers the first command to a designated storage device, and, upon subsequently receiving an instruction for a chip reset from the processor, executes a chip reset, and, upon subsequently receiving a second command from the processor, assigns a tag number belonging to a group which is different from the group used before the chip reset to the second command, and transfers the second command to a designated storage device.Type: GrantFiled: December 10, 2015Date of Patent: March 3, 2020Assignee: HITACHI, LTD.Inventors: Midori Kurokawa, Tsutomu Koga
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Publication number: 20180210677Abstract: Provided is a storage apparatus including a plurality of storage devices which store data, a controller which executes data input/output processing to the storage devices, and a processor which transmits/receives information with the controller, wherein the controller manages a plurality of different tag numbers by separating the tag numbers into a plurality of groups, and upon receiving a first command from the processor, assigns a tag number belonging to one group among the plurality of groups to the first command, and transfers the first command to a designated storage device, and, upon subsequently receiving an instruction for a chip reset from the processor, executes a chip reset, and, upon subsequently receiving a second command from the processor, assigns a tag number belonging to a group which is different from the group used before the chip reset to the second command, and transfers the second command to a designated storage device.Type: ApplicationFiled: December 10, 2015Publication date: July 26, 2018Applicant: HITACHI, LTD.Inventors: Midori KUROKAWA, Tsutomu KOGA
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Publication number: 20180052632Abstract: This storage system includes a processor, a memory, a storage drive, and an interface device. The storage drive determines a size of transfer data based on an offset value which is a value relating to a size between the beginning of a storage area in the memory for the transfer of the data to be transferred to the interface device and the beginning of the partition of the memory to which the beginning of the storage area belongs, and then transfers data to be transferred, which has the determined size, to the interface device. The interface device divides the transferred data into packets and transfers these packets to the processor. The processor then stores the packets transferred from the interface device in the memory on a unit of a partition.Type: ApplicationFiled: May 11, 2015Publication date: February 22, 2018Inventors: Masanori TAKADA, Naoya OKADA, Mitsuo DATE, Tsutomu KOGA
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Patent number: 9495235Abstract: Each transfer route includes an FE I/F out of a plurality of FE I/Fs, a BE I/F out of a plurality of BE I/Fs, at least one memory out of one or more memories, and at least one processor out of one or more processors. I/O target data is transferred via a target transfer route including an FE I/F that has received an I/O request out of a plurality of transfer routes. A processor in the target transfer route generates routing information representing a physical device included in the target transfer route, and transmits a transfer indication including the routing information to at least one of the FE I/F and BE I/F in the target transfer route. In response to the transfer indication, at least one of the FE I/F and BE I/F in the target transfer route adds, to the I/O target data, a guarantee code.Type: GrantFiled: November 18, 2013Date of Patent: November 15, 2016Assignee: HITACHI, LTD.Inventors: Tomoaki Kurihara, Tsutomu Koga, Hideyuki Ihara
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Publication number: 20160246671Abstract: Each transfer route includes an FE I/F out of a plurality of FE I/Fs, a BE I/F out of a plurality of BE I/Fs, at least one memory out of one or more memories, and at least one processor out of one or more processors. I/O target data is transferred via a target transfer route including an FE I/F that has received an I/O request out of a plurality of transfer routes. A processor in the target transfer route generates routing information representing a physical device included in the target transfer route, and transmits a transfer indication including the routing information to at least one of the FE I/F and BE I/F in the target transfer route. In response to the transfer indication, at least one of the FE I/F and BE I/F in the target transfer route adds, to the I/O target data, a guarantee code.Type: ApplicationFiled: November 18, 2013Publication date: August 25, 2016Applicant: HITACHI, LTD.Inventors: Tomoaki KURIHARA, Tsutomu KOGA, Hideyuki IHARA
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Patent number: 8745448Abstract: A storage system comprises a storage device for storing data, a control apparatus which controls the storage device and comprises multiple communication ports, and a switch apparatus which expands the number of storage device couplings and comprises multiple communication ports. Respective multiple communication ports of the control apparatus are coupled to respective multiple communication ports of the switch apparatus, and the switch apparatus is coupled to the storage device. The control apparatus configures at least one communication port of the multiple communication ports of the control apparatus, to a dedicated communication port for outputting only a prescribed command issued when a failure is detected.Type: GrantFiled: June 6, 2012Date of Patent: June 3, 2014Assignee: Hitachi, Ltd.Inventors: Tsutomu Koga, Koji Washiya
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Patent number: 8677181Abstract: A storage apparatus includes a drive unit device including multiple storage drives, a drive interface unit and a power supply unit, a storage controller including multiple processing units and a drive control interface unit, a recording part recording whether a relevant data input/output process was successful for each of multiple data paths, and a failure detection unit performing a process which, when one processing unit determines the data input/output process not being performed successfully, determines whether a result of the data input/output process performed by other processing units is recorded in the recording part within a predetermined period of time after an abnormality of the relevant data input/output process is recorded, and, when the first processing unit detecting the abnormality determines that the data input/output process abnormality is recorded, provides an instruction to stop the data input/output processes to the drive unit device in which the abnormality is detected.Type: GrantFiled: December 13, 2010Date of Patent: March 18, 2014Assignee: Hitachi, Ltd.Inventors: Yosuke Nakayama, Tetsuya Inoue, Tsutomu Koga, Hiroshi Suzuki
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Publication number: 20130332768Abstract: A storage system comprises a storage device for storing data, a control apparatus which controls the storage device and comprises multiple communication ports, and a switch apparatus which expands the number of storage device couplings and comprises multiple communication ports. Respective multiple communication ports of the control apparatus are coupled to respective multiple communication ports of the switch apparatus, and the switch apparatus is coupled to the storage device. The control apparatus configures at least one communication port of the multiple communication ports of the control apparatus, to a dedicated communication port for outputting only a prescribed command issued when a failure is detected.Type: ApplicationFiled: June 6, 2012Publication date: December 12, 2013Applicant: HITACHI, LTD.Inventors: Tsutomu Koga, Koji Washiya
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Patent number: 8560878Abstract: Reduction of data processing capacity attributable to the occurrence of a failure is prevented by promptly identifying the failure location. A storage apparatus includes a plurality of expanders connected to storage media storing data sent from a host system, and a controller for controlling the expanders, wherein the controller sends a failure detection command to the plurality of expanders; the plurality of expanders store the command in their own storage units; and if one expander from among the plurality of expanders detects a failure in another expander immediately following and connected to the one expander, the one expander reads the command stored in a storage unit for the one expander and sends a response including failure detection information corresponding to the command to the controller.Type: GrantFiled: March 23, 2011Date of Patent: October 15, 2013Assignee: Hitachi, Ltd.Inventors: Koji Washiya, Tsutomu Koga, Nobuyuki Minowa
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Patent number: 8402189Abstract: An object is to provide an information processing apparatus capable of improving the availability as a system while improving the reliability of a data transfer path and a data transfer method.Type: GrantFiled: May 13, 2010Date of Patent: March 19, 2013Assignee: Hitachi, Ltd.Inventors: Tsutomu Koga, Yo Iwaoka
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Patent number: 8312325Abstract: One or more switches are interposed between a controller portion and a storage device. When transmission of a command to a certain storage device fails, a command is transmitted starting from an upstream side to a downstream side of a path between the controller portion and the switch to which the certain storage device is connected, and when command transmission fails while transmitting a command from a kth switch (k is an integer of 0 or more) which is connected to a (k+1)th switch and is one level upstream of the (k+1)th switch or from any port of the controller portion, it is determined that a failure has occurred in a power source that supplies power to the (k+1)th switch.Type: GrantFiled: September 8, 2011Date of Patent: November 13, 2012Assignee: Hitachi Ltd.Inventors: Hiroshi Suzuki, Tsutomu Koga, Tetsuya Inoue, Tomokazu Yokoyama, Kenji Jin
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Publication number: 20120246521Abstract: Reduction of data processing capacity attributable to the occurrence of a failure is prevented by promptly identifying the failure location. A storage apparatus includes a plurality of expanders connected to storage media storing data sent from a host system, and a controller for controlling the expanders, wherein the controller sends a failure detection command to the plurality of expanders; the plurality of expanders store the command in their own storage units; and if one expander from among the plurality of expanders detects a failure in another expander immediately following and connected to the one expander, the one expander reads the command stored in a storage unit for the one expander and sends a response including failure detection information corresponding to the command to the controller.Type: ApplicationFiled: March 23, 2011Publication date: September 27, 2012Inventors: Koji Washiya, Tsutomu Koga, Nobuyuki Minowa
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Patent number: 8225036Abstract: A storage controller that can maintain its performance and reduce power consumption and thereby realize large capacity and low power consumption, and a method for controlling such a storage controller are provided. The storage controller includes a plurality of nonvolatile memory modules having a plurality of nonvolatile memory chips for storing data from a host computer, and a nonvolatile memory control unit for controlling data input to and output from the host computer by controlling a power source for the nonvolatile memory modules. When reading or writing data from or to a designated nonvolatile memory module at a specified time in response to a data read/write request from the host computer, the nonvolatile memory control unit controls the power source for only the designated nonvolatile memory module to be turned on.Type: GrantFiled: June 16, 2011Date of Patent: July 17, 2012Assignee: Hitachi, Ltd.Inventor: Tsutomu Koga
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Publication number: 20120151262Abstract: A storage apparatus includes a drive unit device including a plurality of storage drives, a drive interface unit and a power supply unit, the storage drives being configured to provide a physical storage area for creating a logical storage area to be used by an external apparatus, the drive interface unit being configured to input and output data to and from the storage drives, the power supply unit being configured to supply operation power to the storage drives and the drive interface unit, a storage controller including a plurality of processing units and a drive control interface unit, the processing units being configured to perform a data input/output process via the drive interface unit, the data input/output process including a process of writing data from the external apparatus into the storage drives and a process of reading data out of the storage drives, the drive control interface unit being configured to issue a command to the drive interface unit in response to a request from each of the procesType: ApplicationFiled: December 13, 2010Publication date: June 14, 2012Inventors: Yosuke Nakayama, Tetsuya Inoue, Tsutomu Koga, Hiroshi Suzuki
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Publication number: 20110320886Abstract: One or more switches are interposed between a controller portion and a storage device. When transmission of a command to a certain storage device fails, a command is transmitted starting from an upstream side to a downstream side of a path between the controller portion and the switch to which the certain storage device is connected, and when command transmission fails while transmitting a command from a kth switch (k is an integer of 0 or more) which is connected to a (k+1)th switch and is one level upstream of the (k+1)th switch or from any port of the controller portion, it is determined that a failure has occurred in a power source that supplies power to the (k+1)th switch.Type: ApplicationFiled: September 8, 2011Publication date: December 29, 2011Applicant: HITACHI, LTD.Inventors: Hiroshi SUZUKI, Tsutomu KOGA, Tetsuya INOUE, Tomokazu YOKOYAMA, Kenji JIN
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Publication number: 20110283037Abstract: An object is to provide an information processing apparatus capable of improving the availability as a system while improving the reliability of a data transfer path and a data transfer method.Type: ApplicationFiled: May 13, 2010Publication date: November 17, 2011Applicant: HITACHI, LTD.Inventors: Tsutomu Koga, Yo Iwaoka
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Patent number: 8037362Abstract: One or more switches are interposed between a controller portion and a storage device. When transmission of a command to a certain storage device fails, a command is transmitted starting from an upstream side to a downstream side of a path between the controller portion and the switch to which the certain storage device is connected, and when command transmission fails while transmitting a command from a kth switch (k is an integer of 0 or more) which is connected to a (k+1)th switch and is one level upstream of the (k+1)th switch or from any port of the controller portion, it is determined that a failure has occurred in a power source that supplies power to the (k+1)th switch.Type: GrantFiled: August 26, 2010Date of Patent: October 11, 2011Assignee: Hitachi, Ltd.Inventors: Hiroshi Suzuki, Tsutomu Koga, Tetsuya Inoue, Tomokazu Yokoyama, Kenji Jin
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Publication number: 20110246711Abstract: A storage controller that can maintain its performance and reduce power consumption and thereby realize large capacity and low power consumption, and a method for controlling such a storage controller are provided. The storage controller includes: a plurality of nonvolatile memory modules having a plurality of nonvolatile memory chips for storing data from a host computer; and a nonvolatile memory control unit for controlling data input to and output from the host computer by controlling a power source for the nonvolatile memory modules; wherein when reading or writing data from or to a designated nonvolatile memory module at a specified time in response to a data read/write request from the host computer, the nonvolatile memory control unit controls the power source for only the designated nonvolatile memory module to be turned on.Type: ApplicationFiled: June 16, 2011Publication date: October 6, 2011Applicant: HITACHI LTD.Inventor: Tsutomu KOGA
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Patent number: 7996605Abstract: A storage controller and a method for controlling a storage controller, including a plurality of nonvolatile memory modules having a plurality of nonvolatile memory chips for storing data from a host computer and a nonvolatile memory control unit for controlling data input to and output from the host computer by controlling a power source for the nonvolatile memory modules. The nonvolatile memory control unit, when reading or writing data from or to a designated nonvolatile memory module at a specified time in response to a data read/write request from the host computer, controls the power source for only the designated nonvolatile memory module to be turned on that can maintain its performance and reduce power consumption and thereby realize large capacity and low power consumption.Type: GrantFiled: January 30, 2008Date of Patent: August 9, 2011Assignee: Hitachi, Ltd.Inventor: Tsutomu Koga
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Publication number: 20100325484Abstract: One or more switches are interposed between a controller portion and a storage device. When transmission of a command to a certain storage device fails, a command is transmitted starting from an upstream side to a downstream side of a path between the controller portion and the switch to which the certain storage device is connected, and when command transmission fails while transmitting a command from a kth switch (k is an integer of 0 or more) which is connected to a (k+1)th switch and is one level upstream of the (k+1)th switch or from any port of the controller portion, it is determined that a failure has occurred in a power source that supplies power to the (k+1)th switch.Type: ApplicationFiled: August 26, 2010Publication date: December 23, 2010Applicant: HITACHI, LTD.Inventors: Hiroshi SUZUKI, Tsutomu KOGA, Tetsuya INOUE, Tomokazu YOKOYAMA, Kenji JIN