Patents by Inventor Tsutomu Koike
Tsutomu Koike has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9661289Abstract: An RGB video signal is generated by illuminating an object with light from a first monitor and capturing an image of the object with a camera. The second monitor holds a profile representing the correspondence relationship between R, G, and B values generated by displaying an image including values of R, G, and B on a reference monitor and capturing an image of the displayed image with the camera and X, Y, and Z values which are measurements of tristimulus values of the displayed image in the XYZ color space. The second monitor converts the first R, G, and B values of the video signal to first X, Y, and Z values based on the profile, and converts the first X, Y, and Z values to second R, G, and B values appropriate for the second monitor to display an image of the object on a display unit.Type: GrantFiled: July 29, 2016Date of Patent: May 23, 2017Assignee: JVC KENWOOD CORPORATIONInventor: Tsutomu Koike
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Patent number: 9407553Abstract: When a reduction in the transmission speed of the line preset as the TDM line transfer route is detected by a device-connecting line termination unit, a mapping request, to which information indicating the amount of TDM-line bandwidth overflowing from the line and a destination indicating the final line relaying device have been added, is generated by the mapping request processing unit, and transmitted via the other line to another device connected in a ring network in order to map the overflow amount of bandwidth added to the mapping request on each line sequentially from the other device to the line relaying device as the final transfer destination, thereby forming a TDM-line detour route.Type: GrantFiled: September 27, 2012Date of Patent: August 2, 2016Assignee: NEC CORPORATIONInventors: Tsutomu Koike, Shunichi Kumagai
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Patent number: 9104096Abstract: A stereoscopic image display apparatus includes: an image data acquiring unit which acquires two pieces of image data having horizontal parallax; a composition unit which generates display data by composing the two pieces of image data; a line image overlapping unit which overlaps two longitudinal line images with an image based on the display data, and independently moves the two longitudinal line images in a horizontal direction; a parallax information derivation unit which derives parallax information about parallax between the two longitudinal line images; a parallax information overlapping unit which additionally overlaps the parallax information with the image based on the display data; and a display unit which displays the images based on the display data, on which the longitudinal line images and the parallax information are overlapped, such that a producer may easily and accurately identify parallax of each subject image in the display data.Type: GrantFiled: August 27, 2012Date of Patent: August 11, 2015Assignee: JVC KENWOOD CORPORATIONInventor: Tsutomu Koike
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Patent number: 8963928Abstract: Provided is a stereoscopic image processing apparatus allowing a manufacturer of image data to grasp parallax of a subject in display data easily and accurately. The stereoscopic image processing apparatus includes units: acquiring two pieces of image data having horizontal parallax; composing the two pieces of image data to generate display data; deriving parallax of a predetermined object in the two pieces of image data and generates parallax information representing the parallax; holding the generated parallax information in relation to time information assigned to each piece of the image data; generating parallax time image data representing the parallax represented by the parallax information and time represented by the time information as a two-dimensional image; causing the generated parallax time image data and the display data to overlap each other; and displaying the display data overlapping the parallax time image data on a display unit.Type: GrantFiled: March 1, 2012Date of Patent: February 24, 2015Assignee: JVC Kenwood CorporationInventor: Tsutomu Koike
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Publication number: 20140313896Abstract: When a reduction in the transmission speed of the line preset as the TDM line transfer route is detected by a device-connecting line termination unit, a mapping request, to which information indicating the amount of TDM-line bandwidth overflowing from the line and a destination indicating the final line relaying device have been added, is generated by the mapping request processing unit, and transmitted via the other line to another device connected in a ring network in order to map the overflow amount of bandwidth added to the mapping request on each line sequentially from the other device to the line relaying device as the final transfer destination, thereby forming a TDM-line detour route.Type: ApplicationFiled: September 27, 2012Publication date: October 23, 2014Inventors: Tsutomu Koike, Shunichi Kumagai
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Patent number: 8253857Abstract: The portable player is connected to a first connector, and the PC is connected to a second connector. A first connection detecting unit detects whether the portable player is connected, and a second connection detecting unit detects whether the PC is connected. A central processing unit (CPU) switches to a reproduction mode in which an audio signal based on audio data reproduced by the portable player is supplied by the audio processing unit to the speaker, or a PC communication mode in which the portable player and the PC are connected to be in a state in which they can communicate with each other.Type: GrantFiled: February 17, 2010Date of Patent: August 28, 2012Assignee: JVC Kenwood CorporationInventors: Tsutomu Koike, Hiroshi Fujihira
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Patent number: 6767675Abstract: A method of manufacturing a mask includes a mask preparation step of dividing a first desired mask pattern into a first mask pattern part and a second mask pattern part and performing rendering, development and etching on the first and second mask pattern parts independently of each other for preparing a first mask having the first mask pattern part and a second mask having the second mask pattern part independently of each other and a first superposition step of superposing the aforementioned first mask and the aforementioned second mask for combining the first mask pattern part and the second mask pattern part with each other so that the upper surfaces and the lower surfaces of the first and second mask pattern parts are flush with each other respectively thereby forming the aforementioned first desired mask pattern.Type: GrantFiled: May 15, 2002Date of Patent: July 27, 2004Assignee: Renesas Technology Corp.Inventor: Tsutomu Koike
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Publication number: 20030096174Abstract: A method of manufacturing a mask includes a mask preparation step of dividing a first desired mask pattern into a first mask pattern part and a second mask pattern part and performing rendering, development and etching on the first and second mask pattern parts independently of each other for preparing a first mask having the first mask pattern part and a second mask having the second mask pattern part independently of each other and a first superposition step of superposing the aforementioned first mask and the aforementioned second mask for combining the first mask pattern part and the second mask pattern part with each other so that the upper surfaces and the lower surfaces of the first and second mask pattern parts are flush with each other respectively thereby forming the aforementioned first desired mask pattern.Type: ApplicationFiled: May 15, 2002Publication date: May 22, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventor: Tsutomu Koike
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Patent number: 6487711Abstract: A method of analyzing factor responsible errors in a wafer pattern which enables detection of an error ascribable to a difference between mask patterns and an error ascribable to another reason while distinguishing between the errors. A mask pattern is formed by etching a first mask at a first position within an etching chamber. Another mask pattern is formed by etching a second mask at a second position within the etching chamber. A wafer pattern is formed by single shot of exposing radiation through use of the first mask, and another wafer pattern is formed by single shot of exposing radiation through use of the second mask. The size of the wafer pattern formed through use of the first mask and the size of the wafer pattern formed through use of the second mask are compared with each other, thereby detecting a dimensional difference ascribable to a difference between mask patterns and a dimensional difference ascribable to another reason while distinguishing between the dimensional differences.Type: GrantFiled: May 22, 2000Date of Patent: November 26, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Tsutomu Koike
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Patent number: 4924690Abstract: The present invention is to extrude helical internal gears and helical gears by pushing materials processed to any type of blank into a die unit successively by use of a punch, i.e., by passing the materials once through the die unit. The invention is directed to a die unit comprising an outer contour restraining container into which metal material blanks each having a central bore are to be inserted, a die placed contiguously below the container, these container and die being arranged to be circumferentially rotatable relative to each other, and upper and lower mandrels disposed inside the container and the die in alignment with their axes, respectively, and interconnected for being circumferentially rotatable relative to each other, the metal materials being successively pushed into gaps between the upper mandrel and the container and between the lower mandrel and the die by means of a punch to mold helical internal gears.Type: GrantFiled: December 20, 1988Date of Patent: May 15, 1990Assignees: M. H. Center Limited, Hitachi Powdered Metals Co., Ltd.Inventors: Hisanobu Kanamaru, Susumu Aoyama, Tsutomu Koike, Naotatsu Asahi, Yoshiki Hirai
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Patent number: 4653305Abstract: A method and apparatus for cold working a metallic blank having a central hole into a substantially annular or cylindrical article such as an internally and or externally toothed gear, with the method including forcibly inserting a hollow metallic blank at a normal temperature into a die cavity formed between a mandrel placed on a fixed base and a die concentrically surrounding the mandrel so that the blank is plastically deformed between the mandrel and the die; forcibly inserting a subsequent hollow metallic blank into the die cavity while the relative position between the mandrel, the die and the first blank being plastically deformed therebetween is kept unchanged; and urging the subsequent blank against the first blank to extrude the first blank forwardly out of the die whereby the first-said blank is formed into a tubular article.Type: GrantFiled: September 11, 1984Date of Patent: March 31, 1987Assignees: Hitachi, Ltd., M. H. Center, Ltd.Inventors: Hisanobu Kanamaru, Susumu Aoyama, Tsutomu Koike
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Patent number: 4443777Abstract: A small-size transformer comprises an insulative bobbin having a pair of flanges and a hollow center portion on which an insulated tape wire is wound in layers. The center portion of the bobbin is stepped to accommodate a lead wire so that the tape wire is uniformly wound in parallel layers between innermost and outermost layers thereof. A pair of insulative side members each of U-shaped cross section is fitted to the flanges of the bobbin in positions adjacent the outermost winding layer. A core structure has outer arms received in slots of the side members and an inner or center arm accommodated within the hollow center portion of the bobbin. A base is detachably connected to the bobbin and formed with plural vertical slots to firmly secure tubular lead wires therewithin to serve as terminal pins for connection to an associated circuit.Type: GrantFiled: October 14, 1981Date of Patent: April 17, 1984Assignee: Toku Kabushiki KaishaInventor: Tsutomu Koike
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Patent number: 4387418Abstract: A switching regulator is disclosed which is designed so that a negative feedback is applied to the base of a transistor constituting an oscillator adapted for chopping a DC voltage, only during a period of time which is required to effect pulse width control when the transistor is switched from conduction to non-conduction. A control circuit may also be provided which is arranged to compare the output of a current detecting circuit for detecting a current proportional to a current for driving a transformer with the output of an error voltage amplifier for amplifying an output resulting from comparison of a rectified version of the AC output of the transformer with a reference voltage. The foregoing control circuit is also arranged so that when the output of the current detecting circuit exceeds the output of the error amplifier, a trigger signal is imparted to cause the oscillator to be changed from the on state to the off state.Type: GrantFiled: November 14, 1980Date of Patent: June 7, 1983Assignee: Toko, Inc.Inventor: Tsutomu Koike
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Patent number: 4272805Abstract: A switching regulator in which an input DC voltage is chopped and then applied to drive a transformer from which an AC voltage is derived which in turn is rectified in a rectifier circuit, and the output of the rectifier circuit is compared with a first reference voltage so that an output is provided which corresponds to the difference between the two voltages compared with each other and which causes a current to be charged at a capacitor incorporated in a charge-discharge circuit which is arranged to vary the charged current, and the output of the charge-discharge circuit is compared with a second reference voltage so that a trigger signal is produced and applied to the base of a switching transistor only when the output of the charge-discharge circuit exceeds the second reference voltage.Type: GrantFiled: August 13, 1979Date of Patent: June 9, 1981Assignee: Toko, Inc.Inventors: Yasuhide Iguchi, Tsutomu Koike
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Patent number: 4263643Abstract: A switching regulator in which a DC input voltage is chopped by an oscillator applied to a transformer the output of which in turn is rectified by a rectifier circuit; a DC voltage derived from the rectifier is compared with a reference voltage so that a voltage is produced which corresponds to the deviation from said reference voltage of the aforementioned DC voltage derived from the rectifier; the voltage thus produced is amplified by means of an error amplifier; a current proportional to the transformer driving current provided by the oscillator is detected by a current detector; and the output of the error amplifier is compared with the output of the current detector so that only when the former exceeds the latter, a trigger signal is applied to the oscillator, whereby the oscillation of the oscillator is changed from an ON state to an OFF state.Type: GrantFiled: August 30, 1979Date of Patent: April 21, 1981Assignee: Toko, Inc.Inventor: Tsutomu Koike