Patents by Inventor Tsutomu MIYAMAE

Tsutomu MIYAMAE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and semiconductor device examination method
    Patent number: 11740287
    Abstract: A semiconductor device of the embodiment includes a plurality of scan chains, a shift clock control circuit, and a shift clock generation circuit. The plurality of scan chains each include a plurality of scan flip-flops. The shift clock control circuit outputs, to each of the plurality of scan chains, a control signal that non-inverts or inverts a scan clock signal. The shift clock generation circuit is provided to each of the plurality of scan flip-flops and generates a non-inverted scan clock signal or an inverted scan clock signal based on the control signal, the non-inverted scan clock signal being obtained by non-inverting the scan clock signal, the inverted scan clock signal being obtained by inverting the scan clock signal.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: August 29, 2023
    Assignee: Kioxia Corporation
    Inventors: Isao Ooigawa, Nariyuki Fukuda, Kazuhito Hosaka, Tsutomu Miyamae, Takeshi Yamaguchi, Suguru Tahara, Keitarou Mishima, Yuichiro Sanuki, Koichi Kimura
  • SEMICONDUCTOR DEVICE AND SEMICONDUTOR DEVCE EXAMINATION METHOD
    Publication number: 20230079823
    Abstract: A semiconductor device of the embodiment includes a plurality of scan chains, a shift clock control circuit, and a shift clock generation circuit. The plurality of scan chains each include a plurality of scan flip-flops. The shift clock control circuit outputs, to each of the plurality of scan chains, a control signal that non-inverts or inverts a scan clock signal. The shift clock generation circuit is provided to each of the plurality of scan flip-flops and generates a non-inverted scan clock signal or an inverted scan clock signal based on the control signal, the non-inverted scan clock signal being obtained by non-inverting the scan clock signal, the inverted scan clock signal being obtained by inverting the scan clock signal.
    Type: Application
    Filed: March 9, 2022
    Publication date: March 16, 2023
    Applicant: Kioxia Corporation
    Inventors: Isao OOIGAWA, Nariyuki FUKUDA, Kazuhito HOSAKA, Tsutomu MIYAMAE, Takeshi YAMAGUCHI, Suguru TAHARA, Keitarou MISHIMA, Yuichiro SANUKI, Koichi KIMURA
  • Semiconductor circuit
    Patent number: 10311965
    Abstract: According to one embodiment, a semiconductor circuit includes a plurality of memories. The memories are connected to one another in series such that an output node of the memory of the first stage is connected to an input node of the memory of the second stage. The semiconductor circuit includes a test circuit that outputs test data to an input node of the memory of the first stage among the plurality of memories, and a comparison circuit that compares data output from an output node of the memory of the final stage among the plurality of memories with expectation value data.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: June 4, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tsutomu Miyamae, Nariyuki Fukuda, Kazuhito Hosaka, Takeshi Yamaguchi, Suguru Tahara, Isao Ooigawa, Keitarou Mishima, Yuichiro Sanuki
  • SEMICONDUCTOR CIRCUIT
    Publication number: 20180233213
    Abstract: According to one embodiment, a semiconductor circuit includes a plurality of memories. The memories are connected to one another in series such that an output node of the memory of the first stage is connected to an input node of the memory of the second stage. The semiconductor circuit includes a test circuit that outputs test data to an input node of the memory of the first stage among the plurality of memories, and a comparison circuit that compares data output from an output node of the memory of the final stage among the plurality of memories with expectation value data.
    Type: Application
    Filed: August 30, 2017
    Publication date: August 16, 2018
    Inventors: Tsutomu MIYAMAE, Nariyuki FUKUDA, Kazuhito HOSAKA, Takeshi YAMAGUCHI, Suguru TAHARA, Isao OOIGAWA, Keitarou MISHIMA, Yuichiro SANUKI