Patents by Inventor Tsutomu Murase

Tsutomu Murase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory cell array with improved substrate current pathway
    Patent number: 9842853
    Abstract: A semiconductor memory device according to an embodiment includes a first semiconductor layer containing an acceptor and a memory cell array including an interlayer insulating layer and a conductive layer arranged in a first direction above the first semiconductor layer and a memory columnar body extending in the first direction and having a lower end positioned lower than a position of a top surface of the first semiconductor layer, the memory columnar body containing a second semiconductor layer in a columnar shape having a side face opposite to a side face of the conductive layer, wherein a first portion of the first semiconductor layer in contact with the side face of the memory columnar body contains a donor in a higher concentration than a second portion different from the first portion of the first semiconductor substrate.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: December 12, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Mitsuru Sato, Shigeki Kobayashi, Tsutomu Murase
  • SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20170077121
    Abstract: A semiconductor memory device according to an embodiment includes a first semiconductor layer containing an acceptor and a memory cell array including an interlayer insulating layer and a conductive layer arranged in a first direction above the first semiconductor layer and a memory columnar body extending in the first direction and having a lower end positioned lower than a position of a top surface of the first semiconductor layer, the memory columnar body containing a second semiconductor layer in a columnar shape having a side face opposite to a side face of the conductive layer, wherein a first portion of the first semiconductor layer in contact with the side face of the memory columnar body contains a donor in a higher concentration than a second portion different from the first portion of the first semiconductor substrate.
    Type: Application
    Filed: December 16, 2015
    Publication date: March 16, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mitsuru SATO, Shigeki Kobayashi, Tsutomu Murase