Abstract: A semiconductor device includes three integrated circuits. One of the integrated circuits includes: a first connector configured to connect to a device; and a transmitter. The transmitter is configured to transmit to another integrated circuit, first data on each of a plurality of pieces of packet data. The transmitter is also configured to, when the first connector is connected to the device, while a second controller is performing a second process, transmit, to a first controller, a request to process data transmitted from the device.

Abstract: An information processing apparatus includes a first integrated circuit including a first controller that processes data acquired from a device and that controls an operation of the device; a second integrated circuit including a second controller with a higher processing speed than a processing speed of the first controller; and a third integrated circuit including a first connection unit connectable to the device. The third integrated circuit includes a second connection unit connectable to the first integrated circuit, a third connection unit connectable to the second integrated circuit, and a setting unit that, when the device is connected to the first connection unit, sets an integrated circuit to be connected, in accordance with a communication speed of the connected device.

Abstract: An information processing apparatus includes a volatile memory that stores data, a controller that controls an operation of a device, an interface that temporarily stores data input from the device, a writing unit that controls writing of the data on the volatile memory, a first communication pathway that connects the interface to the writing unit and is used to transmit the data acquired by the interface to the volatile memory and to transfer the data written on the volatile memory, a second communication pathway that connects the interface to the writing unit and does not share a route with the first communication pathway, and a switching unit that switches a communication path used to transmit data from the interface to the volatile memory from the first communication pathway to the second communication pathway if the interface has received image data from the device.

Abstract: An information processing apparatus includes a first integrated circuit and a second integrated circuit. The first integrated circuit includes a first controller which processes data obtained from a device and which controls operations of the device. The second integrated circuit includes a second controller whose data processing speed is faster than the data processing speed of the first controller. When the second controller performs a second process with greater priority than a first process after start of the first process and before completion of the first process, the second controller determines whether or not the first controller is to restart the first process on the basis of a condition defined as to data subjected to the first process.

Abstract: An information processing apparatus includes a first integrated circuit including a first controller that processes data acquired from a device and that controls an operation of the device; a second integrated circuit including a second controller with a higher processing speed than a processing speed of the first controller; and a third integrated circuit including a first connection unit connectable to the device. The third integrated circuit includes a second connection unit connectable to the first integrated circuit, a third connection unit connectable to the second integrated circuit, and a setting unit that, when the device is connected to the first connection unit, sets an integrated circuit to be connected, in accordance with a communication speed of the connected device.

Abstract: An information processing apparatus includes a volatile memory that stores data, a controller that controls an operation of a device, an interface that temporarily stores data input from the device, a writing unit that controls writing of the data on the volatile memory, a first communication pathway that connects the interface to the writing unit and is used to transmit the data acquired by the interface to the volatile memory and to transfer the data written on the volatile memory, a second communication pathway that connects the interface to the writing unit and does not share a route with the first communication pathway, and a switching unit that switches a communication path used to transmit data from the interface to the volatile memory from the first communication pathway to the second communication pathway if the interface has received image data from the device.

Abstract: An information processing apparatus includes a memory that is volatile, a memory controller connected to the memory in an information exchangeable manner, and a clock enable (CKE) controller. The CKE controller controls a CKE signal in response to a request for a proxy in self-refresh control, the CKE signal being transmitted from the memory controller to the memory and being controlled to be kept low until cancellation of the proxy is requested. At a time of shifting to a power-saving mode, the memory controller stores information held by a central processing unit (CPU) in the memory and causes the memory to shift to a self-refresh mode. At a time of recovery from the power-saving mode, the memory controller requests the CKE controller for the cancellation of the proxy in the self-refresh control and thereafter cancels the self-refresh mode of the memory.

Abstract: An information processing apparatus includes a memory that is volatile, a memory controller connected to the memory in an information exchangeable manner, and a clock enable (CKE) controller. The CKE controller controls a CKE signal in response to a request for a proxy in self-refresh control, the CKE signal being transmitted from the memory controller to the memory and being controlled to be kept low until cancellation of the proxy is requested. At a time of shifting to a power-saving mode, the memory controller stores information held by a central processing unit (CPU) in the memory and causes the memory to shift to a self-refresh mode. At a time of recovery from the power-saving mode, the memory controller requests the CKE controller for the cancellation of the proxy in the self-refresh control and thereafter cancels the self-refresh mode of the memory.

Abstract: An information processing device includes a computing unit and a display unit. The computing unit computes a power consumption per a predetermined time during a power saving mode that reduces power consumption, on the basis of a count per type of an interrupt signal produced during the power saving mode, and a power consumption pre-estimated per type of the interrupt signal. The display unit displays a power consumption computed by the computing unit using generated or stored electric power.

Abstract: A processing control apparatus includes a processor, a setting unit, and a delay unit. The processor operates by using power supplied from a main power supply, and executes a process on the basis of received information. The setting unit restricts power supply from the main power supply to the processor, and sets a restricted period in which a process is prohibited from being executed in the processor. In the case where a specific process which is being executed when the restricted period is to start will be completed within a predetermined allowed time period, the delay unit delays the time when the restricted period is start at least until the specific process is completed.

Abstract: An information processing device includes a computing unit and a display unit. The computing unit computes a power consumption per a predetermined time during a power saving mode that reduces power consumption, on the basis of a count per type of an interrupt signal produced during the power saving mode, and a power consumption pre-estimated per type of the interrupt signal. The display unit displays a power consumption computed by the computing unit using generated or stored electric power.

Abstract: A display control device includes a display device, a detector, and a prohibiting unit. The display device displays a consumed power value indicating power consumed by a processing section that operates on power supplied from a principal power source section. The detector operates on power from an auxiliary power source section that is different from the principal power source section to detect presence or absence of a mobile body within an area determined in advance. The prohibiting unit prohibits the display device from displaying the consumed power value for a period for which the detector is not detecting a mobile body or a part of the period.

Abstract: A processing control apparatus includes a processor, a setting unit, and a delay unit. The processor operates by using power supplied from a main power supply, and executes a process on the basis of received information. The setting unit restricts power supply from the main power supply to the processor, and sets a restricted period in which a process is prohibited from being executed in the processor. In the case where a specific process which is being executed when the restricted period is to start will be completed within a predetermined allowed time period, the delay unit delays the time when the restricted period is start at least until the specific process is completed.

Abstract: A power saving processing apparatus that includes a processing unit, an output unit and a transition unit is provided. The processing unit is configured to transition from a first state where power is supplied to a second state where power supply is restricted, executes a first process required for such transition before transition from the first state to the second state, and executes a second process to output a first signal after executing the first process. The output unit outputs a second signal after receiving the first signal output from the processing unit, and outputs the second signal when not receiving the first signal output from the processing unit within a predetermined time period after a predetermined time after the first process starts. The transition unit transitions the processing unit to the second state after receiving the second signal output from the output unit.

Abstract: A power saving processing apparatus that includes a processing unit, an output unit and a transition unit is provided. The processing unit is configured to transition from a first state where power is supplied to a second state where power supply is restricted, executes a first process required for such transition before transition from the first state to the second state, and executes a second process to output a first signal after executing the first process. The output unit outputs a second signal after receiving the first signal output from the processing unit, and outputs the second signal when not receiving the first signal output from the processing unit within a predetermined time period after a predetermined time after the first process starts. The transition unit transitions the processing unit to the second state after receiving the second signal output from the output unit.