Patents by Inventor Tsutomu Ogino

Tsutomu Ogino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11960225
    Abstract: An image forming apparatus includes, an image forming portion configured to form a toner image on a sheet using printing toner and apply powder adhesive on the sheet, a fixing portion configured to heat the toner image formed on the sheet and the powder adhesive applied on the sheet by the image forming portion and fix the toner image and the powder adhesive to the sheet, and a bonding portion configured to bond the sheet with the powder adhesive by reheating the sheet having been heated by the fixing portion. The bonding portion is arranged above the image forming portion.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: April 16, 2024
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Koji Yamaguchi, Kohei Matsuda, Hiroki Ogino, Yasushi Katsuta, Kaori Noguchi, Junko Hirata, Akira Kuroda, Yuki Nishizawa, Tsutomu Shimano, Toru Oguma
  • Patent number: 9536966
    Abstract: A semiconductor device includes a III-N layer, a plurality of parallel conductive fingers on the III-N layer, an insulator layer over the III-N layer, and a gate. The plurality of parallel conductive fingers includes a source and drain bus, a plurality of source fingers coupled to the source bus and extending from the source bus towards the drain bus to respective source finger ends, and a plurality of drain fingers coupled to the drain bus and extending from the drain bus towards the source bus to respective drain finger ends, the drain fingers being interdigitated between the source fingers. The gate comprises a plurality of straight and a plurality of connecting sections, each straight section between a source finger and adjacent drain finger, and the connecting sections each joining two adjacent straight sections and curving around a respective source or drain finger end.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: January 3, 2017
    Assignee: Transphorm Inc.
    Inventor: Tsutomu Ogino
  • Publication number: 20160172480
    Abstract: A semiconductor device includes a III-N layer, a plurality of parallel conductive fingers on the III-N layer, an insulator layer over the III-N layer, and a gate. The plurality of parallel conductive fingers includes a source and drain bus, a plurality of source fingers coupled to the source bus and extending from the source bus towards the drain bus to respective source finger ends, and a plurality of drain fingers coupled to the drain bus and extending from the drain bus towards the source bus to respective drain finger ends, the drain fingers being interdigitated between the source fingers. The gate comprises a plurality of straight and a plurality of connecting sections, each straight section between a source finger and adjacent drain finger, and the connecting sections each joining two adjacent straight sections and curving around a respective source or drain finger end.
    Type: Application
    Filed: December 15, 2015
    Publication date: June 16, 2016
    Inventor: Tsutomu Ogino
  • Patent number: 6091475
    Abstract: Proposed is a novel connector for display inspection of a liquid crystal display panel, by which the display panel per se can be inspected before mounting of a driver IC chip thereon to greatly improve the productivity of the display inspection.
    Type: Grant
    Filed: December 9, 1997
    Date of Patent: July 18, 2000
    Assignee: Shin-Etsu Polymer Co., Ltd.
    Inventors: Tsutomu Ogino, Hiroto Komatsu
  • Patent number: 5960536
    Abstract: Proposed is a novel wiring circuit board for mounting of a semiconductor chip suitable for free mounting and demounting thereof. The wiring circuit board comprises: an insulating base plate provided with electrodes on one surface and having an opening for insertion of the semiconductor chip; bonding wires each connected to one of the electrodes at one end, with the other end appearing in the opening at a position just to come into contact with the electrode of a semiconductor chip inserted into the opening; and a resinous encapsulating layer covering the opening and embedding the bonding wires. A method for the preparation of this wiring circuit board is also disclosed in which accurate positioning of the ends of the bonding wires appearing in the opening of the base plate is accomplished by using a dummy chip provided with etching-resistant false electrodes and inserted into the opening followed by subsequent removal by etching after completion of the bonding work of the bonding wires.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: October 5, 1999
    Assignee: Shin-Etsu Polymer Co., Ltd.
    Inventors: Tsutomu Ogino, Hiroto Komatsu