Patents by Inventor Tsutomu Onaro

Tsutomu Onaro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9559654
    Abstract: Disclosed is a power amplification module which has a comparatively small size and is capable of adjusting the rising characteristic of a gain. The power amplification module includes a first gain control current generation circuit which generates a first gain control current changing with a control voltage, a first bias current generation circuit which generates a first bias current according to the first gain control current, a gain control voltage generation circuit which generates a gain control voltage changing with the control voltage, a first transistor which is emitter-grounded and in which an input signal and the first bias current are supplied to a base thereof, and a second transistor which is cascode-connected to the first transistor and in which the gain control voltage is supplied to a base thereof and a first output signal obtained by amplifying the input signal is output from a collector thereof.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: January 31, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hayato Nakamura, Mitsuo Ariie, Tadashi Matsuoka, Tsutomu Onaro
  • Publication number: 20150130537
    Abstract: Disclosed is a power amplification module which has a comparatively small size and is capable of adjusting the rising characteristic of a gain. The power amplification module includes a first gain control current generation circuit which generates a first gain control current changing with a control voltage, a first bias current generation circuit which generates a first bias current according to the first gain control current, a gain control voltage generation circuit which generates a gain control voltage changing with the control voltage, a first transistor which is emitter-grounded and in which an input signal and the first bias current are supplied to a base thereof, and a second transistor which is cascode-connected to the first transistor and in which the gain control voltage is supplied to a base thereof and a first output signal obtained by amplifying the input signal is output from a collector thereof.
    Type: Application
    Filed: October 22, 2014
    Publication date: May 14, 2015
    Inventors: Hayato Nakamura, Mitsuo Ariie, Tadashi Matsuoka, Tsutomu Onaro