Patents by Inventor Tsutomu Onishi

Tsutomu Onishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240134720
    Abstract: An apparatus including a processor, with processing circuitry configured to obtain a parameter at a time when a system call function is called by a system call; call a first system call function from a kernel, and returning a processing result of the first system call function, when a processing target in the first system call function to be called that is indicated by the parameter is not a monitoring target that affects an identity of data to be protected; and return a result as in a case where processing by the first system call function is successfully executed, or a processing result indicating an error, without calling the first system call function, when the processing target in the first system call function to be called that is indicated by the parameter is the monitoring target.
    Type: Application
    Filed: December 11, 2023
    Publication date: April 25, 2024
    Applicant: DIGITAL INFORMATION TECHNOLOGIES CORPORATION
    Inventors: Noritaka IIJIMA, Tsutomu NAKAJIMA, Koji ONISHI
  • Patent number: 7700400
    Abstract: The present invention can finely arrange p+-type diffusion layers and n+-type diffusion layers. A p+-type diffusion layer 2 and an n+-type diffusion layer 3 are simultaneously formed on a back surface 1a of a semiconductor substrate 1 in a state that the p+-type diffusion layer 2 and the n+-type diffusion layer 3 are arranged close to each other, and a back surface 1a side of the semiconductor substrate 1 on which outer end portions of the p+-type diffusion layers 2 and the n+-type diffusion layers 3 are brought into contact with each other is removed thus separating the p+-type diffusion layer 2 and the n+-type diffusion layer 3 from each other and hence, the p+-type diffusion layer 2 and the n+-type diffusion layer 3 can be separately arranged in a state that the p+-type diffusion layer 2 and the n+-type diffusion layer 3 are arranged close to each other.
    Type: Grant
    Filed: October 21, 2005
    Date of Patent: April 20, 2010
    Assignees: Naoetsu Electronics Co., Ltd., Shin-Etsu Chemical Co., Ltd.
    Inventors: Tsutomu Onishi, Takeshi Akatsuka, Shunichi Igarashi
  • Publication number: 20090020158
    Abstract: The present invention is a method for manufacturing a solar cell by forming a p-n junction in a semiconductor substrate having a first conductivity type, wherein, at least: a first coating material containing a dopant and an agent for preventing a dopant from scattering, and a second coating material containing a dopant, are coated on the semiconductor substrate having the first conductivity type so that the second coating material may be brought into contact with at least the first coating material; and, a first diffusion layer formed by coating the first coating material, and a second diffusion layer formed by coating the second coating material the second diffusion layer having a conductivity is lower than that of the first diffusion layer are simultaneously formed by a diffusion heat treatment; a solar cell manufactured by the method; and a method for manufacturing a semiconductor device.
    Type: Application
    Filed: April 11, 2006
    Publication date: January 22, 2009
    Applicants: SHIN-ETSU HANDOTAI CO., LTD., NAOETSU ELECTRONICS CO., LTD., SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Hiroyuki Ohtsuka, Masatoshi Takahashi, Naoki Ishikawa, Shigenori Saisu, Toyohiro Ueguri, Satoyuki Ojima, Takenori Watabe, Takeshi Akatsuka, Tsutomu Onishi
  • Publication number: 20070264746
    Abstract: The present invention can finely arrange p+-type diffusion layers and n+-type diffusion layers. A p+-type diffusion layer 2 and an n+-type diffusion layer 3 are simultaneously formed on a back surface 1a of a semiconductor substrate 1 in a state that the p+-type diffusion layer 2 and the n+-type diffusion layer 3 are arranged close to each other, and a back surface la side of the semiconductor substrate 1 on which outer end portions of the p+-type diffusion layers 2 and the n+-type diffusion layers 3 are brought into contact with each other is removed thus separating the p+-type diffusion layer 2 and the n+-type diffusion layer 3 from each other and hence, the p+-type diffusion layer 2 and the n+-type diffusion layer 3 can be separately arranged in a state that the p+-type diffusion layer 2 and the n+-type diffusion layer 3 are arranged close to each other.
    Type: Application
    Filed: October 21, 2005
    Publication date: November 15, 2007
    Applicants: NAOETSU ELECTRONICS CO., LTD., SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Tsutomu Onishi, Takeshi Akatsuka, Shunichi Igarashi
  • Patent number: 4179955
    Abstract: A power wrench, or clamping tool, for tightening a bolt, nut and the like comprising a power shaft engaging the bolt, nut and the like, a driving power source of electromotive, pneumatic or hydraulic type, an anti-reaction force member for the prevention of rotation of the tool case due to the reaction force, a harmonic drive mechanism as the speed reduction mechanism between the power shaft and the driving power source, planetary gear device provided between the harmonic drive mechanism and the power shaft, a first mechanism engaged with a nut screwed to a torque set bolt and rotating the nut with the rotation of the power shaft thereby tightening the nut, a second mechanism engaged to the torque set bolt in such a way as to break the torque set bolt at a predetermined position when the tightening torque arrives at a predetermined value in the course of the clamping and a knock out mechanism which discharges the broken piece of the torque set bolt out of the case by means of a spring force.
    Type: Grant
    Filed: August 1, 1978
    Date of Patent: December 25, 1979
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Kabushiki Kaisha Terauchi Seisakusho
    Inventors: Toshio Akiyoshi, Tsutomu Onishi, Shozo Haikawa
  • Patent number: 4106371
    Abstract: A clamping or power wrench tool for tightening a bolt, nut and the like comprising a power shaft engaging the bolt, nut and the like, a driving power source of electromotive, pneumatic or hydraulic type, an anti-reaction force member for the prevention of rotation of the tool case due to the reaction force, a harmonic drive mechanism as the speed reduction mechanism between the power shaft and the driving power source, planetary gear device provided between the harmonic drive mechanism and the power shaft, a first mechanism engaged with a nut screwed to a torque set bolt and rotating the nut with the rotation of the power shaft thereby tightening the nut, a second mechanism engaged to the torque set bolt in such a way as to break the torque set bolt at a predetermined position when the tightening torque arrives at a predetermined value in the course of the clamping and a knock out mechanism which discharges the broken piece of the torque set bolt out of the case by means of a spring force.
    Type: Grant
    Filed: February 17, 1977
    Date of Patent: August 15, 1978
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Kabushiki Kaisha Terauchi Seisakusho
    Inventors: Toshio Akiyoshi, Tsutomu Onishi, Shozo Haikawa