Patents by Inventor Tsutomu Oosuka

Tsutomu Oosuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10804203
    Abstract: The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: October 13, 2020
    Assignee: Pannova Semic
    Inventors: Tsutomu Oosuka, Hisashi Ogawa, Yoshihiro Sato
  • Publication number: 20170345760
    Abstract: The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.
    Type: Application
    Filed: August 17, 2017
    Publication date: November 30, 2017
    Inventors: Tsutomu Oosuka, Hisashi Ogawa, Yoshihiro Sato
  • Patent number: 9780039
    Abstract: The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: October 3, 2017
    Assignee: PANNOVA SEMIC, LLC
    Inventors: Tsutomu Oosuka, Hisashi Ogawa, Yoshihiro Sato
  • Publication number: 20160163649
    Abstract: The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.
    Type: Application
    Filed: February 2, 2016
    Publication date: June 9, 2016
    Inventors: Tsutomu Oosuka, Hisashi Ogawa, Yoshihiro Sato
  • Patent number: 9287392
    Abstract: The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: March 15, 2016
    Assignee: Pannova Semic, LLC
    Inventors: Tsutomu Oosuka, Hisashi Ogawa, Yoshihiro Sato
  • Patent number: 9086046
    Abstract: An ignition apparatus is provided with a Zener diode as a limiter device, which limits a primary voltage of an ignition coil to be less than a Zener voltage, and a switching circuit, which prohibits a limiter function of the Zener diode at a start of discharge and switches the limiter device to perform the limiter function for a predetermined time period following the start of discharge. A secondary voltage is limited to be more than a secondary limit value. Even when blowout arises in discharging, re-discharging is avoided from arising immediately after the blowout and exhaustion of a spark plug caused by repetition of discharging is avoided.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: July 21, 2015
    Assignee: DENSO CORPORATION
    Inventors: Yuji Kajita, Masamichi Shibata, Yasuomi Imanaka, Atsuya Mizutani, Tsutomu Oosuka
  • Patent number: 8558321
    Abstract: A semiconductor device includes: a first MIS transistor of a first conductivity type having a first active region as a region of a semiconductor substrate surrounded by an element isolation region formed in an upper portion of the semiconductor substrate, a first gate insulating film having a first high dielectric film formed on the first active region, and a first gate electrode formed on the first gate insulating film; and a resistance element having a second high dielectric film formed on the element isolation region and a resistance layer made of silicon formed on the second high dielectric film. The first high dielectric film and the second high dielectric film include the same high dielectric material, and the first high dielectric film includes a first adjustment metal, but the second high dielectric film does not include the first adjustment metal.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: October 15, 2013
    Assignee: Panasonic Corporation
    Inventors: Hiroji Shimizu, Yoshihiro Sato, Hideyuki Arai, Takayuki Yamada, Tsutomu Oosuka
  • Patent number: 8350332
    Abstract: A first and second gate electrodes are formed on a first and second active regions, respectively. The first and second gate electrodes have a first and second metal-containing conductive films, respectively. The first and second metal-containing conductive films are formed on the isolation region for segmenting the first and second active regions to be spaced apart from each other. A third metal-containing conductive film, which is a part of each of the first and second gate electrodes, is continuously formed from a top of the first metal-containing conductive film through a top of the isolation region to a top of the second metal-containing conductive film. The third metal-containing conductive film is in contact with the first and second metal-containing conductive films.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: January 8, 2013
    Assignee: Panasonic Corporation
    Inventors: Tsutomu Oosuka, Yoshihiro Sato, Hisashi Ogawa
  • Patent number: 8344455
    Abstract: The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: January 1, 2013
    Assignee: Panasonic Corporation
    Inventors: Tsutomu Oosuka, Hisashi Ogawa, Yoshihiro Sato
  • Publication number: 20110227168
    Abstract: The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.
    Type: Application
    Filed: May 31, 2011
    Publication date: September 22, 2011
    Applicant: Panasonic Corporation
    Inventors: Tsutomu Oosuka, Hisashi Ogawa, Yoshihiro Sato
  • Publication number: 20110169100
    Abstract: A semiconductor device includes: a first MIS transistor of a first conductivity type having a first active region as a region of a semiconductor substrate surrounded by an element isolation region formed in an upper portion of the semiconductor substrate, a first gate insulating film having a first high dielectric film formed on the first active region, and a first gate electrode formed on the first gate insulating film; and a resistance element having a second high dielectric film formed on the element isolation region and a resistance layer made of silicon formed on the second high dielectric film. The first high dielectric film and the second high dielectric film include the same high dielectric material, and the first high dielectric film includes a first adjustment metal, but the second high dielectric film does not include the first adjustment metal.
    Type: Application
    Filed: January 12, 2011
    Publication date: July 14, 2011
    Inventors: Hiroji SHIMIZU, Yoshihiro Sato, Hideyuki Arai, Takayuki Yamada, Tsutomu Oosuka
  • Patent number: 7977800
    Abstract: The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: July 12, 2011
    Assignee: Panasonic Corporation
    Inventors: Tsutomu Oosuka, Hisashi Ogawa, Yoshihiro Sato
  • Publication number: 20100059827
    Abstract: A first and second gate electrodes are formed on a first and second active regions, respectively. The first and second gate electrodes have a first and second metal-containing conductive films, respectively. The first and second metal-containing conductive films are formed on the isolation region for segmenting the first and second active regions to be spaced apart from each other. A third metal-containing conductive film, which is a part of each of the first and second gate electrodes, is continuously formed from a top of the first metal-containing conductive film through a top of the isolation region to a top of the second metal-containing conductive film. The third metal-containing conductive film is in contact with the first and second metal-containing conductive films.
    Type: Application
    Filed: November 16, 2009
    Publication date: March 11, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Tsutomu OOSUKA, Yoshihiro Sato, Hisashi Ogawa
  • Publication number: 20090108379
    Abstract: The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.
    Type: Application
    Filed: October 8, 2008
    Publication date: April 30, 2009
    Inventors: Tsutomu OOSUKA, Hisashi OGAWA, Yoshihiro SATO