Abstract: A content addressable memory according to the present invention includes plural index generators, an output unit, and a controller. The plural index generators generates a signature of an input vector using plural hash functions, and to generate index corresponding to the input vector by searching registered information for a registered vector based on the signature. The output unit combines each output of the plural index generators to produce the index corresponding to the input vector. The controller configured to control an update of the registered information.

Abstract: A content addressable memory according to the present invention includes plural index generators, an output unit, and a controller. The plural index generators generates a signature of an input vector using plural hash functions, and to generate index corresponding to the input vector by searching registered information for a registered vector based on the signature. The output unit combines each output of the plural index generators to produce the index corresponding to the input vector. The controller configured to control an update of the registered information.

Abstract: To provide a device to reconfigure multi-level logic networks, which enable logic modification and reconfiguration of a multi-level logic network with small circuit area and low-power dissipation in a simple manner. For example, in the case of reconfiguring a multi-level logic network following logic modification for deleting an output vector F(b) of an objective logic function F(X) corresponding to an input vector b, unmodified pq elements are selected one by one from the nearest pq element EG to an output side. At this time, among output values of pq elements closer to an input side than selected pq elements, output values corresponding to the input vector, which equal an output value corresponding to any input variable X other than the input vector b are considered modified and thus not selected. Then, a selected output value corresponding to the input vector b is rewritten to an “invalid value”.

Abstract: The associative memory comprises a simplified functional processing unit (SFPU), implemented by an LUT logic network, that implements simplified CAM function g, where g is the function derived from CAM function ƒ by replacing the value showing “invalid” with the don't care, an auxiliary memory that stores the inverse function ƒ?1 of said CAM function ƒ; and an output modifier that checks whether the output value of said SFPU is equal to the output value of the CAM function ƒ; wherein the SFPU produces the operational value (“tentative index value”) for the simplified CAM function g; the auxiliary memory produces the value of the inverse function ƒ?1 when the tentative index value is applied; the output modifier compares the input data with the value of the inverse function ƒ?1, and produces the output of said SFPU if they are the same, otherwise produces the signal showing the “invalid”.

Abstract: The address generator has a hash network for producing hashed Y1, which is obtained by hushing X1, to an input vector X=(X1, X2), a tentative address generator Y1 for making an address generation function f(X) to a tentative address A? when no hash collision occurs and otherwise making one of unique addresses A to A?, a data regenerator for producing X?=f?1(A?), a unique address generator for producing A? when X? coincides with X and otherwise producing “invalid value”, a complementary address generator for producing (X) to X, to which the unique address generator produces “invalid value”, and otherwise producing “invalid value”, and an output combiner which produces, when the outputs of the unique address generator and the complementary address generator have values other than the “invalid value”, the values as a unique address A and otherwise produces “invalid value” as A.

Abstract: To provide a device to reconfigure multi-level logic networks, which enable logic modification and reconfiguration of a multi-level logic network with small circuit area and low-power dissipation in a simple manner. For example, in the case of reconfiguring a multi-level logic network following logic modification for deleting an output vector F(b) of an objective logic function F(X) corresponding to an input vector b, unmodified pq elements are selected one by one from the nearest pq element EG to an output side. At this time, among output values of pq elements closer to an input side than selected pq elements, output values corresponding to the input vector, which equal an output value corresponding to any input variable X other than the input vector b are considered modified and thus not selected. Then, a selected output value corresponding to the input vector b is rewritten to an “invalid value”.

Abstract: A device for logic synthesis that can be used to synthesize LUT logic circuit having intermediate outputs for multiple-output logic functions.

Abstract: The address generator has a hash network for producing hashed Y1, which is obtained by hushing X1, to an input vector X=(X1, X2), a tentative address generator Y1 for making an address generation function f(X) to a tentative address A? when no hash collision occurs and otherwise making one of unique addresses A to A?, a data regenerator for producing X?=f?1(A?), a unique address generator for producing A? when X? coincides with X and otherwise producing “invalid value”, a complementary address generator for producing (X) to X, to which the unique address generator produces “invalid value”, and otherwise producing “invalid value”, and an output combiner which produces, when the outputs of the unique address generator and the complementary address generator have values other than the “invalid value”, the values as a unique address A and otherwise produces “invalid value” as A.

Abstract: The associative memory comprises a simplified functional processing unit (SFPU), implemented by an LUT logic network, that implements simplified CAM function g, where g is the function derived from CAM function ƒ by replacing the value showing “invalid” with the don't care, an auxiliary memory that stores the inverse function ƒ?1 of said CAM function ƒ; and an output modifier that checks whether the output value of said SFPU is equal to the output value of the CAM function ƒ; wherein the SFPU produces the operational value (“tentative index value”) for the simplified CAM function g; the auxiliary memory produces the value of the inverse function ƒ?1 when the tentative index value is applied; the output modifier compares the input data with the value of the inverse function ƒ?1, and produces the output of said SFPU if they are the same, otherwise produces the signal showing the “invalid”.

Abstract: The PLD that can change the number of input lines and the number of rail between the memories for logic according to the objective logic function, and to which the optimum design can be done to make the size of memory minimum. The memories for logic (4) are arranged in series, and LUT is memorized in them. The input variables are input from the external input lines to each memories for logic (4). The interconnection circuit (5) connects the output lines or the external input lines of memory for logic (4) in the preceding stage and the input lines of memory for logic (4) of the succeeding stage between two memories for logic (4), according to the information for connection memorized in memory for interconnections (6). By rewriting the information for connection according to the objective logic function, the interconnection circuit can be reconfigured, and the number of input lines and the number of rail can be changed.

Abstract: The invention relates to a connector (10) for connecting welding torch where the connector comprises a connector body (12) made of electrically insulating material, a cylindrical current transferring body (30) fitted on the cylindrical front part (13) of the connector body (12), made of electrically conductive material, where the current transferring body (30) has a threaded surface (32) and a side contact surface (35) besides the threaded surface (32) on its side surface, a threaded bore (37) on the side contact surface (35) for fixing current cable with screwed joint and a frontal contact surface (33), further an attachment bracket (60), made of electrically insulating plastic, the attachment bracket (60) has a sleeve part (62), which encircles space apart the threaded surface (32) and the sleeve part (62) has a flange (64) protruding from its front part for fixing, the flange (64) is provided with one or more holes (65) in it.

Abstract: The object of the present invention is to present a device for logic synthesis that can be used to synthesize LUT logic circuit having intermediate outputs for multiple-output logic functions.