Patents by Inventor Tsutomu Shimayama
Tsutomu Shimayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220393132Abstract: A light-emitting element and a display device capable of improving the light emission property are provided. Each of a plurality of anode electrodes (11) is provided for a corresponding pixel. The pixel-isolating insulation film (12) has an opening (120) exposing corresponding one of the plurality of anode electrodes (11) to outside, and has an eave (123B) in the middle of a thickness direction of an inner wall of the opening (120). An organic layer (13) includes a CGL (132) cut by the eave (123B) of the pixel-isolating insulation film (12), and covers the opening (120). A cathode electrode (14) is disposed on a surface of the organic layer (13), the surface being a surface on the opposite side of the anode electrode (11).Type: ApplicationFiled: October 16, 2020Publication date: December 8, 2022Inventors: Tomotaka Nishikawa, Kunihiko Hikichi, Yuuki Sakai, Tsutomu Shimayama
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Patent number: 11462600Abstract: A display device of the present disclosure includes a plurality of recess portions provided on a pixel formation surface, and a pixel arranged in each of the plurality of recess portions, in which a light-emitting unit of the pixel is formed on a side wall and a bottom surface of each of the plurality of recess portions. A manufacturing method of a display device of the present disclosure is a manufacturing method of a display device having the above-described configuration. Furthermore, an electronic device of the present disclosure is an electronic device including a display device having the above-described configuration.Type: GrantFiled: April 23, 2019Date of Patent: October 4, 2022Assignee: Sony Semiconductor Solutions CorporationInventor: Tsutomu Shimayama
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Publication number: 20210057499Abstract: A display device of the present disclosure includes a plurality of recess portions provided on a pixel formation surface, and a pixel arranged in each of the plurality of recess portions, in which a light-emitting unit of the pixel is formed on a side wall and a bottom surface of each of the plurality of recess portions. A manufacturing method of a display device of the present disclosure is a manufacturing method of a display device having the above-described configuration. Furthermore, an electronic device of the present disclosure is an electronic device including a display device having the above-described configuration.Type: ApplicationFiled: April 23, 2019Publication date: February 25, 2021Inventor: Tsutomu Shimayama
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Patent number: 9601054Abstract: There is provided a display device including a pixel array unit in which a plurality of pixels are arrayed in a matrix shape. A predetermined amount of light emission variation is added to a light emission state of each pixel and a cycle of the light emission state of the pixel array unit in the case of the addition is shorter than the cycle of a light emission state of the pixel array unit before the predetermined amount of light emission variation is added.Type: GrantFiled: May 8, 2013Date of Patent: March 21, 2017Assignee: JOLED INC.Inventor: Tsutomu Shimayama
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Patent number: 9231037Abstract: A display unit includes a first substrate and a second substrate opposed to each other, a display element having a first electrode and a second electrode on the first substrate, an auxiliary electrode provided on a surface facing the first substrate of the second substrate, and including a plurality of films stacked in a direction from the second substrate to the first substrate, and a plurality of pillars configured to electrically connect the auxiliary electrode to the second electrode.Type: GrantFiled: September 16, 2014Date of Patent: January 5, 2016Assignee: JOLED Inc.Inventor: Tsutomu Shimayama
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Publication number: 20150108512Abstract: A display unit includes a first substrate and a second substrate opposed to each other, a display element having a first electrode and a second electrode on the first substrate, an auxiliary electrode provided on a surface facing the first substrate of the second substrate, and including a plurality of films stacked in a direction from the second substrate to the first substrate, and a plurality of pillars configured to electrically connect the auxiliary electrode to the second electrode.Type: ApplicationFiled: September 16, 2014Publication date: April 23, 2015Inventor: Tsutomu Shimayama
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Publication number: 20150097494Abstract: There is provided a display device including a pixel array unit in which a plurality of pixels are arrayed in a matrix shape. A predetermined amount of light emission variation is added to a light emission state of each pixel and a cycle of the light emission state of the pixel array unit in the case of the addition is shorter than the cycle of a light emission state of the pixel array unit before the predetermined amount of light emission variation is added.Type: ApplicationFiled: May 8, 2013Publication date: April 9, 2015Inventor: Tsutomu Shimayama
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Patent number: 8981368Abstract: A thin film transistor includes: a gate electrode, a source electrode, and a drain electrode; an oxide semiconductor layer provided on one side of the gate electrode with an insulating film in between, the oxide semiconductor layer being provided in a region not facing the source electrode and the drain electrode and being electrically connected to the source electrode and the drain electrode; and a low resistance oxide layer provided in a region facing the source electrode and in a region facing the drain electrode, the regions being adjacent to the oxide semiconductor layer, and the low resistance oxide layer having an electric resistivity lower than an electric resistivity of the oxide semiconductor layer.Type: GrantFiled: January 2, 2013Date of Patent: March 17, 2015Assignee: Sony CorporationInventors: Tsutomu Shimayama, Nobutoshi Fujii, Takashige Fujimori
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Patent number: 8828886Abstract: Disclosed is a low dielectric constant insulating film formed of a polymer containing Si atoms, O atoms, C atoms, and H atoms, which includes straight chain molecules in which a plurality of basic molecules with an SiO structure are linked in a straight chain, binder molecules with an SiO structure linking a plurality of the straight chain molecules. The area ratio of a signal indicating a linear type SiO structure is 49% or more, and the signal amount of the signal indicating Si(CH3) is 66% or more.Type: GrantFiled: April 5, 2012Date of Patent: September 9, 2014Assignee: Tohoku UniversityInventors: Seiji Samukawa, Shigeo Yasuhara, Shingo Kadomura, Tsutomu Shimayama, Hisashi Yano, Kunitoshi Tajima, Noriaki Matsunaga, Masaki Yoshimaru
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Patent number: 8759222Abstract: Disclosed herein is a method for fabrication of semiconductor device involving a first step of coating the substrate with a double-layered insulating film in laminate structure having the skeletal structure of inorganic material and a second step of etching the upper layer of the insulating film as far as the lower layer of the insulating film. In the method for fabrication of semiconductor device, the first step is carried out in such a way that the skeletal structure is incorporated with a pore-forming material of hydrocarbon compound so that one layer of the insulating film contains more carbon than the other layer of the insulating film.Type: GrantFiled: March 1, 2007Date of Patent: June 24, 2014Assignee: Sony CorporationInventors: Tsutomu Shimayama, Takatoshi Kameshima, Masaki Okamoto
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Publication number: 20120190212Abstract: Disclosed is a low dielectric constant insulating film formed of a polymer containing Si atoms, O atoms, C atoms, and H atoms, which includes straight chain molecules in which a plurality of basic molecules with an SiO structure are linked in a straight chain, binder molecules with an SiO structure linking a plurality of the straight chain molecules. The area ratio of a signal indicating a linear type SiO structure is 49% or more, and the signal amount of the signal indicating Si(CH3) is 66% or more.Type: ApplicationFiled: April 5, 2012Publication date: July 26, 2012Inventors: Seiji SAMUKAWA, Shigeo Yasuhara, Shingo Kadomura, Tsutomu Shimayama, Hisashi Yano, Kunitoshi Tajima, Noriaki Matsunaga, Masaki Yoshimaru
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Patent number: 7602061Abstract: Disclosed herein is a semiconductor device including: an insulating film configured to be provided on a substrate and be porosified through decomposition and removal of a pore-forming material; a covering insulating film configured to be provided on the insulating film; and conductive layer patterns configured to be provided in the covering insulating film and the insulating film and reach the substrate, wherein the insulating film includes a non-porous region in which the pore-forming material remains.Type: GrantFiled: August 29, 2007Date of Patent: October 13, 2009Assignee: Sony CorporationInventors: Yoshihisa Kagawa, Tsutomu Shimayama, Takatoshi Kameshima
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Patent number: 7569498Abstract: A manufacturing method of a semiconductor device, includes forming a porous organo-siloxane film containing a porogen component having carbon as a main component above a semiconductor substrate, forming an upper-side insulating film having at least one of film density and film composition different from that of the porous organo-siloxane film on the porous organo-siloxane film, and applying at least one of an electron beam and an ultraviolet ray to the porous organo-siloxane film and upper-side insulating film to cause polymerization reaction of the porogen component in the porous organo-siloxane film.Type: GrantFiled: January 25, 2008Date of Patent: August 4, 2009Assignees: Kabushiki Kaisha Toshiba, Sony CorporationInventors: Hideaki Masuda, Hideshi Miyajima, Tsutomu Shimayama
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Publication number: 20080254631Abstract: Disclosed herein is a method for fabrication of semiconductor device involving a first step of coating the substrate with a double-layered insulating film in laminate structure having the skeletal structure of inorganic material and a second step of etching the upper layer of the insulating film as far as the lower layer of the insulating film. In the method for fabrication of semiconductor device, the first step is carried out in such a way that the skeletal structure is incorporated with a pore-forming material of hydrocarbon compound so that one layer of the insulating film contains more carbon than the other layer of the insulating film.Type: ApplicationFiled: March 1, 2007Publication date: October 16, 2008Inventors: Tsutomu Shimayama, Takatoshi Kameshima, Masaki Okamoto
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Publication number: 20080194117Abstract: A manufacturing method of a semiconductor device, includes forming a porous organo-siloxane film containing a porogen component having carbon as a main component above a semiconductor substrate, forming an upper-side insulating film having at least one of film density and film composition different from that of the porous organo-siloxane film on the porous organo-siloxane film, and applying at least one of an electron beam and an ultraviolet ray to the porous organo-siloxane film and upper-side insulating film to cause polymerization reaction of the porogen component in the porous organo-siloxane film.Type: ApplicationFiled: January 25, 2008Publication date: August 14, 2008Inventors: Hideaki Masuda, Hideshi Miyajima, Tsutomu Shimayama
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Publication number: 20080054454Abstract: Disclosed herein is a semiconductor device including: an insulating film configured to be provided on a substrate and be porosified through decomposition and removal of a pore-forming material; a covering insulating film configured to be provided on the insulating film; and conductive layer patterns configured to be provided in the covering insulating film and the insulating film and reach the substrate, wherein the insulating film includes a non-porous region in which the pore-forming material remains.Type: ApplicationFiled: August 29, 2007Publication date: March 6, 2008Applicant: SONY CORPORATIONInventors: Yoshihisa Kagawa, Tsutomu Shimayama, Takatoshi Kameshima
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Publication number: 20060199373Abstract: A manufacturing method of a semiconductor device, comprising providing a low-relative-dielectric-constant film above a substrate containing at least oxygen and having a relative dielectric constant of 3.3 or more, a conductor being to be buried in the film, performing a plasma processing by discharging a gas containing a noble gas as a main component to the film, the plasma processing being executed while the substrate above which the film is provided is storing in a processing chamber having an inside covered with a material composed of an element except for oxygen and substantially set under an oxygen-free atmosphere, and providing a first insulating film above the low-relative-dielectric-constant film by a plasma CVD method, being made of a material containing at least one of a material containing oxygen and a material containing an element reacting with oxygen, a conductor being to be buried in the first insulating film.Type: ApplicationFiled: February 24, 2006Publication date: September 7, 2006Inventors: Hideshi Miyajima, Hideaki Masuda, Tsutomu Shimayama, Shunichi Shibuki
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Publication number: 20050150452Abstract: The present invention provides a process kit for a semiconductor processing chamber. The processing chamber is a vacuum processing chamber that includes a chamber body defining an interior processing region. The processing region receives a substrate for processing, and also supports equipment pieces of the process kit. The process kit includes a pumping liner configured to be placed within the processing region of the processing chamber, and a C-channel liner configured to be placed along an outer diameter of the pumping liner. The pumping liner and the C-channel liner have novel interlocking features designed to inhibit parasitic pumping of processing or cleaning gases from the processing region. The invention further provides a semiconductor processing chamber having an improved process kit, such as the kit described. In one arrangement, the chamber is a tandem processing chamber.Type: ApplicationFiled: January 14, 2004Publication date: July 14, 2005Inventors: Soovo Sen, Mark Fodor, Martin Seamons, Priya Kulkarni, Visweswaren Sivaramakrishnan, Sudha Rathi, Tsutomu Shimayama, Thomas Nowak, Wendy Yeh
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Patent number: 6855644Abstract: The present invention provides a deposition method and deposition apparatus capable of forming a fluorine-containing silicon inorganic insulating film of stable film properties and a method of manufacturing a semiconductor device. Deposition apparatus 10 comprises parallel plate type electrodes 16, 22 arranged within reaction chamber 12, gas supply sources 20, 32, 34 for feeding process gas containing SiH4, SiF4 and oxygen source substance into reaction chamber 12, valves 36, 38, 40, gas mixing chamber 28 and power source 44 that supplies RF power for generating the plasma of the process gas. In this deposition apparatus 10, power source 44 is capable of supplying RF power of at least 1000 Watts to parallel plate type electrodes 16, 22. In this apparatus 10, fluorine-containing silicon oxide film is deposited on wafer 14 by generating the plasma of process gas containing SiH4, SiF4 and N2O.Type: GrantFiled: October 23, 2001Date of Patent: February 15, 2005Assignee: Applied Materials Inc.Inventors: Yoichi Suzuki, Tsutomu Shimayama
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Publication number: 20020048969Abstract: The present invention provides a deposition method and deposition apparatus capable of forming a fluorine-containing silicon inorganic insulating film of stable film properties and a method of manufacturing a semiconductor device. Deposition apparatus 10 comprises parallel plate type electrodes 16, 22 arranged within reaction chamber 12, gas supply sources 20, 32, 34 for feeding process gas containing SiH4, SiF4 and oxygen source substance into reaction chamber 12, valves 36, 38, 40, gas mixing chamber 28, and power source 44 that supplies RF power for generating the plasma of the process gas. In this deposition apparatus 10, power source 44 is capable of supplying RF power of at least 1000 Watts to parallel plate type electrodes 16, 22. In this apparatus 10, fluorine-containing silicon oxide film is deposited on wafer 14 by generating the plasma of process gas containing SiH4, SiF4 and N2O.Type: ApplicationFiled: October 23, 2001Publication date: April 25, 2002Applicant: Applied Materials, Inc.Inventors: Yoichi Suzuki, Tsutomu Shimayama