Abstract: A polymer bushing includes: an inner conductor; a hard insulating tube; a shielding metal fitting; a polymer covering that includes a body part that covers an outer periphery of the insulating tube, and a plurality of umbrella-shaped sheds that are formed at an outer periphery of the body part; and an electric-field stress-control layer that is composed of a zinc oxide layer or a high-permittivity layer, and is disposed along an interface between the insulating tube and the polymer covering. A rear end part of the electric-field stress-control layer is connected to the shielding metal fitting. The body part includes a first body part that has a uniform thickness, and a second body part that is located in a region around a front end part of the electric-field stress-control layer and has a thickness greater than the thickness of the first body part.

Abstract: A polymer bushing includes: an inner conductor; a hard insulating tube; a shielding metal fitting; a polymer covering that includes a body part that covers an outer periphery of the insulating tube, and a plurality of umbrella-shaped sheds that are formed at an outer periphery of the body part; and an electric-field stress-control layer that is composed of a zinc oxide layer or a high-permittivity layer, and is disposed along an interface between the insulating tube and the polymer covering. A rear end part of the electric-field stress-control layer is connected to the shielding metal fitting. The body part includes a first body part that has a uniform thickness, and a second body part that is located in a region around a front end part of the electric-field stress-control layer and has a thickness greater than the thickness of the first body part.

Abstract: When the longitudinal central axis line of a first linear wave-guide 2 that receives light is set to be a reference line, open portions of circular arcs of first curved wave-guides 4a, 4b that are coupled to a tapered wave-guide 3 face outward when viewed from the reference line. On the other hand, open portions of circular arcs of second curved wave-guides 5a, 5b that are coupled to the first curved wave-guides 4a, 4b face inward when viewed from the reference line. Furthermore, second linear wave-guides 6a, 6b, which are coupled to the first linear wave-guide through the first and second curved wave-guides, and the reference line X are outwardly coupled to form an angle, which is set to be greater than 0 degree. According to the present invention, there can be provided a branch optical wave-guide that can make its entire length short with polarization property of respective output ports equalized.

Abstract: A semiconductor integrated circuit device such as a memory device with logic function comprises a plurality of RAM macrocells and gate arrays. The RAM macrocells are constituted by bipolar CMOS RAMs having a total memory capacity of at least 100 kilobits, and the gate arrays contain at least 4000 gates. The logic circuits in the memory device with logic function or the like are constructed by selectively combining CMOS, bipolar CMOS or ECL gate circuits depending on the output load capacity, transmission characteristic requirement, power dissipation and required layout area. The level of signals at various circuits is set to the ECL level or MOS level depending on the local circuit configuration and other factors. The memory device further incorporates sequence control circuits required to be installed downstream of buffer storages of computers.

Abstract: A semiconductor integrated circuit device such as a memory device with logic function comprises a plurality of RAM macrocells and gate arrays. The RAM macrocells are constituted by bipolar CMOS RAMs having a total memory capacity of at least 100 kilobits, and the gate arrays contain at least 4000 gates. The logic circuits in the memory device with logic function or the like are constructed by selectively combining CMOS, bipolar CMOS or ECL gate circuits depending on the output load capacity, transmission characteristic requirement, power dissipation and required layout area. The level of signals at various circuits is set to the ECL level or MOS level depending on the local circuit configuration and other factors. The memory device further incorporates sequence control circuits required to be installed downstream of buffer storages of computers.

Abstract: When an IOP is transferring data at the maximal throughput because of the fact that the input-output processor (IOP) has issued a next request under a state when the request buffers are full of requests from the IOP at least a part of the requests from the instruction processor (IP) is inhibited. Inhibition of the requests from the IP is released when the pitch of the requests from the IOP reaches a predetermined period or more. When the IOP is transferring data at the maximal throughput in a system having a cache memory, access to the main memory by the IP is inhibited in case requested data does not exist in the cache memory.

Abstract: A memory access control system for an information processing apparatus having a buffer memory and a main memory wherein when a store or access request is generated, in the case where the data block in the address to be accessed does not exist in the buffer memory, the store requested data from a data register is written into the buffer memory before the first data in the data block read out from the main memory is written into the buffer memory, and the data register is released to receive the next request.