Abstract: An object of the present invention is to realize a memory cell including a single polysilicon layer so as to simplify the fabrication process, improve the productivity and lower the fabrication cost of the memory cell. Another object of the present invention is to realize a memory cell with a simple structure as well as to reduce the area of the memory cell so as to attain high integration. Still another object of the present invention is to form a fine memory cell by utilizing DHE (drain channel hot electrons) and GIDL (gate induced drain leakage). An EEPROM memory cell 10 includes a substrate 12; a source region 14 and a drain region 16 formed on a surface of the substrate 12; a channel region 18 defined on the surface of the substrate 12 between the source region 14 and the drain region 16; a gate oxide film 20 formed on the channel region 18 so as to partly overlap with the source region 14 and the drain region 16; and a gate 22 including polysilicon formed on the gate oxide film 20.