Abstract: A test control device includes a test variable generation device and a test processing device. The test variable generation device uses a test prediction model to generate a first manipulated variable based on a difference between a target value and a first controlled variable value from a device under test. The test processing device acquires a second controlled variable value from the device under based on use of the first manipulated variable value. The test variable generation device notifies the device under test of end of a test if the second controlled variable value is equal to or greater than the target value or uses the test prediction model to generate a second manipulated variable based on a difference between the target value and the second controlled variable value when the second controlled variable value is less than the target value.

Abstract: A memory management device of an example of the invention controls writing into and reading from a main memory including a nonvolatile semiconductor memory and a volatile semiconductor memory in response to a writing request and a reading request from a processor. The memory management device includes a coloring information storage unit that stores coloring information generated based on a data characteristic of write target data to be written into at least one of the nonvolatile semiconductor memory and the volatile semiconductor memory, and a writing management unit that references the coloring information to determines a region into which the write target data is written from the nonvolatile semiconductor memory and the volatile semiconductor memory.

Abstract: A memory management device of an example of the invention controls writing into and reading from a main memory including a nonvolatile semiconductor memory and a volatile semiconductor memory in response to a writing request and a reading request from a processor. The memory management device includes a coloring information storage unit that stores coloring information generated based on a data characteristic of write target data to be written into at least one of the nonvolatile semiconductor memory and the volatile semiconductor memory, and a writing management unit that references the coloring information to determines a region into which the write target data is written from the nonvolatile semiconductor memory and the volatile semiconductor memory.

Abstract: According to one embodiment, a program causes a processor to perform providing, by a fault injection module, cooperation information to a debug function. The program causes a processor to perform receiving, by the fault injection module, a notification of at least one of condition related information and action related information as a response to the cooperation information from the debug function. The program causes a processor to perform determining, by the fault injection module, at least one of a fault injection condition and a fault injection action based on the notification. The program causes a processor to perform creating, by the fault injection module, a fault injection scenario that defines a fault injection procedure with respect to the fault injection target based on at least one of the determined fault injection condition and fault injection action.

Abstract: According to one embodiment, a memory management device includes a history management unit, an address translation table, an address management unit, and a data management unit. The history management unit manages an access history for data stored in a nonvolatile semiconductor memory. The address translation table includes a translation table of a logical address and a physical address corresponding to the data. The address management unit specifies, based on the access history, second data to be accessed after access to first data being stored in the nonvolatile semiconductor memory, and registers a second physical address corresponding to the second data in the address translation table in association with a first logical address corresponding to the first data. The data management unit reads out the second data from the nonvolatile semiconductor memory to a buffer.

Abstract: A pseudo-error generating device of an embodiment includes error injection information including a header section and a data section, a storage section configured to store the error injection information, and at least one error injecting circuit, connected to a test target circuit through a predetermined path, configured to inject a pseudo-error to the predetermined path. The header section includes a port specifying one of the at least one error injecting circuit, and an address specifying the data section. The data section includes an injection condition and error injection data for injecting the pseudo-error. The error injecting circuit injects the pseudo-error to the predetermined path based on the injection condition and the error injection data.

Abstract: A test apparatus of the present embodiment has a logic cell, a host and a first bus. The host includes: a conversion section configured to analyze a test vector and convert the test vector to signal control data and a waveform shape; and a judgment section configured to analyze an expected value comparison result to perform success/failure judgment of a test of a semiconductor circuit. The logic cell is provided with a first storage section configured to store the signal control data, a second storage section configured to store the waveform shape as a waveform shape table, a waveform generating section configured to generate an output waveform for controlling the semiconductor circuit and output the output waveform, and an expected value comparing section configured to obtain the expected value comparison result on the basis of the signal control data and the waveform shape table.

Abstract: According to one embodiment, an information processing device includes a first determination section and a setting section. The first determination section determines inconsistency between first data and second data. The first data is stored in a nonvolatile semiconductor memory. The second data is corresponding to the first data and stored in a semiconductor memory. The setting section sets execution timing of write back based on access frequency information associated with the second data.

Abstract: A memory management device of an example of the invention controls writing into and reading from a main memory including a nonvolatile semiconductor memory and a volatile semiconductor memory in response to a writing request and a reading request from a processor. The memory management device includes a coloring information storage unit that stores coloring information generated based on a data characteristic of write target data to be written into at least one of the nonvolatile semiconductor memory and the volatile semiconductor memory, and a writing management unit that references the coloring information to determines a region into which the write target data is written from the nonvolatile semiconductor memory and the volatile semiconductor memory.

Abstract: According to one embodiment, a semiconductor device includes a NAND flash memory, an error correction unit, and a table. The NAND flash memory is configured to hold data. The error correction unit detects and corrects errors in the data. The table holds information on an error correction method associated with each piece of data. The error correction unit selects an error correction method to be applied for each piece of data in accordance with the information in the table.

Abstract: According to one embodiment, a memory management device includes a history management unit, an address translation table, an address management unit, and a data management unit. The history management unit manages an access history for data stored in a nonvolatile semiconductor memory. The address translation table includes a translation table of a logical address and a physical address corresponding to the data. The address management unit specifies, based on the access history, second data to be accessed after access to first data being stored in the nonvolatile semiconductor memory, and registers a second physical address corresponding to the second data in the address translation table in association with a first logical address corresponding to the first data. The data management unit reads out the second data from the nonvolatile semiconductor memory to a buffer.

Abstract: According to one embodiment, an information processing device includes a first determination section and a setting section. The first determination section determines inconsistency between first data and second data. The first data is stored in a nonvolatile semiconductor memory. The second data is corresponding to the first data and stored in a semiconductor memory. The setting section sets execution timing of write back based on access frequency information associated with the second data.

Abstract: According to one embodiment, an interface control apparatus controls an interface to which a calibration is required in use. The interface control apparatus includes an interface controller configured to drive the interface, a storage device that stores a predicted value of a setting value after the calibration is carried out on the interface, the setting value to be set to the interface controller, and a setting unit configured to set the setting value to the interface controller based on the predicted value stored in the storage device.