Patents by Inventor Tsutomu Wakimoto

Tsutomu Wakimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8400131
    Abstract: A voltage converter circuit can include a boost converter having a switching transistor and configured to receive an input voltage, produce an output voltage and selectively operate in one of a boost mode, a skip mode and a linear mode. In the boost and skip modes, the boost converter can switch on and off the switching transistor at a switching frequency to produce an output voltage at magnitudes greater than input voltage magnitudes. In the linear mode, the boost converter can turn off the switching transistor at all times to pass the input voltage unboosted to produce an output voltage at magnitudes less than input voltage magnitudes.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: March 19, 2013
    Assignee: Analog Devices, Inc.
    Inventors: Hongxing Li, Tsutomu Wakimoto
  • Patent number: 8390491
    Abstract: Embodiments of the present invention may provide an integrated circuit that may comprise a first transistor to receive an input voltage signal at its gate and generate an output voltage signal at its drain. Further, the integrated circuit may comprise a second transistor to form an active load of the first transistor, the second transistor may have its drain and gate coupled to the drain of the first transistor. In addition, the integrated circuit may comprise a third transistor to form a current mirror with the second transistor, a fourth transistor to form an active load of the third transistor, and a fifth transistor to form a current mirror with the fourth transistor. The fifth transistor may be connected to the drain of the second transistor. The integrated circuit may form an amplifier and Gm stage of a reference buffer.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: March 5, 2013
    Assignee: Analog Devices, Inc.
    Inventor: Tsutomu Wakimoto
  • Publication number: 20120182167
    Abstract: Embodiments of the present invention may provide an integrated circuit that may comprise a first transistor to receive an input voltage signal at its gate and generate an output voltage signal at its drain. Further, the integrated circuit may comprise a second transistor to form an active load of the first transistor, the second transistor may have its drain and gate coupled to the drain of the first transistor. In addition, the integrated circuit may comprise a third transistor to form a current mirror with the second transistor, a fourth transistor to form an active load of the third transistor, and a fifth transistor to form a current mirror with the fourth transistor. The fifth transistor may be connected to the drain of the second transistor. The integrated circuit may form an amplifier and Gm stage of a reference buffer.
    Type: Application
    Filed: January 14, 2011
    Publication date: July 19, 2012
    Applicant: ANALOG DEVICES, INC.
    Inventor: Tsutomu WAKIMOTO
  • Publication number: 20110221412
    Abstract: A voltage converter circuit can include a boost converter having a switching transistor and configured to receive an input voltage, produce an output voltage and selectively operate in one of a boost mode, a skip mode and a linear mode. In the boost and skip modes, the boost converter can switch on and off the switching transistor at a switching frequency to produce an output voltage at magnitudes greater than input voltage magnitudes. In the linear mode, the boost converter can turn off the switching transistor at all times to pass the input voltage unboosted to produce an output voltage at magnitudes less than input voltage magnitudes.
    Type: Application
    Filed: March 9, 2010
    Publication date: September 15, 2011
    Applicant: ANALOG DEVICES, INC.
    Inventors: Hongxing LI, Tsutomu WAKIMOTO
  • Patent number: 5745003
    Abstract: A multi-level driver circuit comprises: (a) an output buffer; (b) a first switch for applying a first analog level to the output buffer when in a closed state; (c) a second switch for applying a second analog level to the output buffer when in a closed state; (d) a third switch for applying a third analog level to the output buffer when in a closed state, wherein the third switch applies to the output buffer a capacitance which is dependent upon level when the third switch is in an open state and is unclamped; and (e) a clamping circuit for clamping the third switch such that the third switch applies to the output buffer a capacitance which is substantially independent of the third analog level when the third switch is in an open state and is clamped by the clamping circuit. The switches can be solid-state switches, such as diode bridges. Any number of switches can be provided, and more than one of the switches can be provided with a clamping circuit.
    Type: Grant
    Filed: September 11, 1996
    Date of Patent: April 28, 1998
    Assignee: Schlumberger Technologies Inc.
    Inventors: Tsutomu Wakimoto, Toshihiro Nomura
  • Patent number: 4885548
    Abstract: Wideband amplifier having a differential amplifier or single-ended amplifier and having a capacitaqnce compensation circuit is disclosed. The amplifier detects the voltage variations of a signal input node or a signal output node, generates a compensation current equal in magnitude and opposite in direction to a current flowing in a parasitic capacitance such as a transistor junction capacitance, and cancels the parasitic capacitance associated with a node by supplying the compensation current in a reverse phase to the node to which the parasitic capacitance is attached. As a result, a wideband amplifier is achieved, and it can also be used as a high-speed comparator. Further, harmonic distortions causing from the voltage dependency of the parasitic capacitance can be reduced by flowing the compensation current corresponding to a voltage impressed to the junction capacitance.
    Type: Grant
    Filed: July 20, 1988
    Date of Patent: December 5, 1989
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Tsutomu Wakimoto, Yukio Akazawa