Patents by Inventor Tsutomu YOSHIDOME

Tsutomu YOSHIDOME has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD FOR LAYOUT VERIFICATION OF SEMICONDUCTOR INTEGRATED CIRCUIT
    Publication number: 20110088006
    Abstract: A method for verifying a match between layout patterns of elements provided in a semiconductor integrated circuit, includes a verification condition setting step of setting a verification condition including information about paired elements whose layout patterns should match each other, a layout data input step of inputting layout data including pattern information and arrangement information of the paired elements, and a mismatched pattern parameter calculation layout verifying step of comparing the layout patterns of the paired elements based on the verification condition and the layout data to calculate a distance between the paired elements and at least one mismatched pattern.
    Type: Application
    Filed: December 16, 2010
    Publication date: April 14, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Seijiro KOJIMA, Masaomi TOYAMA, Tsutomu YOSHIDOME, Masanori ITO