Patents by Inventor Tsuyoshi Chimura

Tsuyoshi Chimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020171490
    Abstract: The object of this invention is to realize high-speed rise and/or fall characteristics for amplifier without increasing transistor size or current consumption. A first rise sensing circuit 42 and a second a sensing circuit 44 are connected to main circuit 40. The first sensing circuit 42 has a PMOS transistor which functions as a rise sensing transistor, a pair of NMOS transistors 48 and 50, which form a current-mirror circuit, and a PMOS transistor 52, which drives the PMOS transistor 46 used for speed up in main circuit 40. The second sensing circuit 44 has a PMOS transistor 54, which functions as a fall sensing transistor, a pair of NMOS transistors 56 and 58, which form a current-mirror circuit, and a PMOS transistor 60 used for driving the PMOS transistor used for speed up in main circuit 40.
    Type: Application
    Filed: May 16, 2001
    Publication date: November 21, 2002
    Inventor: Tsuyoshi Chimura
  • Patent number: 6483384
    Abstract: The object of this invention is to realize high-speed rise and/or fall characteristics for amplifier without increasing transistor size or current consumption. A first rise sensing circuit 42 and a second a sensing circuit 44 are connected to main circuit 40. The first sensing circuit 42 has a PMOS transistor which functions as a rise sensing transistor, a pair of NMOS transistors 48 and 50, which form a current-mirror circuit, and a PMOS transistor 52, which drives the PMOS transistor 46 used for speed up in main circuit 40. The second sensing circuit 44 has a PMOS transistor 54, which functions as a fall sensing transistor, a pair of NMOS transistors 56 and 58, which form a current-mirror circuit, and a PMOS transistor 60 used for driving the PMOS transistor used for speed up in main circuit 40.
    Type: Grant
    Filed: May 16, 2001
    Date of Patent: November 19, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Tsuyoshi Chimura
  • Patent number: 5818295
    Abstract: An operational amplifier with improved operational speed, as well as low power consumption, arranges a current mirror made of the pMOS transistors PT.sub.17 and PT.sub.18 in the stage after the initial-stage differential amplifier, supplies the output of the initial-stage differential amplifier to the gate of the nMOS transistor NT.sub.14, supplies the current flowing through the current mirror to the output stage side by a current mirror made of the pMOS transistors PT.sub.15 and PT.sub.16, and lastly a pMOS transistor PT.sub.19 is connected as a constant-current source between the supply line for the power supply voltage V.sub.DD and the node ND.sub.12, and makes the idling current I.sub.19 flow in the node ND.sub.12. Due to this, stabilization of DC operations during normal states and when shifting its states can be designed without considering the characteristics in the vicinity of the threshold voltage of pMOS transistor PT.sub.
    Type: Grant
    Filed: July 1, 1996
    Date of Patent: October 6, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Tsuyoshi Chimura, Masahiko Higashi, Tatsumi Satoh