Patents by Inventor Tsuyoshi Etoh

Tsuyoshi Etoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210287395
    Abstract: An information processing system includes a storage device that stores therein a trained model, and a processor. The trained model is trained to output a position and shape of an object in a training image based on training data. The training data is data in which the training image is provided with an annotation indicating the position and shape of the object. The training image is an image captured with an angle of view including the object whose position and shape are not clearly displayed in an image. The processor executes detection processing on a detection image to output detected information indicating the position and shape of the object. The processor then causes a display device to display the detected information superimposed on the detection image.
    Type: Application
    Filed: May 28, 2021
    Publication date: September 16, 2021
    Applicants: OLYMPUS CORPORATION, National University Corporation OITA UNIVERSITY, Fukuoka Institute of Technology
    Inventors: Makoto Ishikake, Toshiya Kamiyama, Masafumi Inomata, Tsuyoshi Etoh, Yukio Iwashita, Makoto Nakashima, Tatsushi Tokuyasu, Yusuke Matsunobu
  • Publication number: 20120072877
    Abstract: According to one embodiment, a layout verification apparatus includes a design section, a layout creation section, a first verification section and a second verification section. One of the first and second verification sections includes a filter processing section which executes a filter processing of a verification target element to be verified by a mask data used to a manufacture of the semiconductor integrated circuit, and the verification target element to be verified needs an ion implantation. The filter processing section comprises a first logic section which executes an logical AND of the verification target element to be verified, a mask data necessary in order to form the verification target element to be verified, and a data inverted a mask data unnecessary in order to form the verification target element to be verified.
    Type: Application
    Filed: September 12, 2011
    Publication date: March 22, 2012
    Inventors: Hideki TAKAHASHI, Tsuyoshi Etoh, Tomohito Kawano, Tatsuya Hiramatsu, Kiyoharu Murakami, Kouji Nakao
  • Patent number: 5659512
    Abstract: A semiconductor integrated circuit includes a cell matrix having a large number of DRAM cells in a matrix shape; a plurality of bit line pairs which have a plurality of bit lines; a plurality of bit line differential amplifier circuits each provided in each pair of bit lines for amplifying a potential difference between the first and second bit lines; a pair of data lines for receiving a charge transmission from the bit line pairs and having a first data line connected to the first bit lines and a second data line connected to the second bit lines; a switch circuit for turning on/off the charge transmission from each bit line pair to the data line pair; a data line differential amplifier circuit for amplifying the potential difference between the first and second bit lines of the data line pair; and an amplitude limiting circuit including a transistor which has a source electrode connected to anyone of the first and second data lines, a drain electrode connected to the other of the first and second data lines
    Type: Grant
    Filed: March 13, 1996
    Date of Patent: August 19, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Koyanagi, Tsuyoshi Etoh
  • Patent number: 5375092
    Abstract: In order to enable enlargement/reduction of data with a simple structure in a first-in first-out memory device thereby reducing the circuit scale of this device, output terminals (Q.sub.0 to Q.sub.3) of a read clock counter (16) are shifted to low order digits and connected to input terminals (A.sub.0 to A.sub.2) of a read address decoder (18). The read clock counter (16) and a read data sense amplifier (19) operate in response to read clocks (RK2). Enlarged read data (RD) are outputted from the read data sense amplifier (19). It is possible to implement enlargement/reduction of data by changing connection between the read clock counter (16) and the read address decoder (18), thereby remarkably simplifying the circuit structure of the first-in first-out memory device having an enlargement/reduction function.
    Type: Grant
    Filed: June 8, 1993
    Date of Patent: December 20, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masaharu Taniguchi, Tsuyoshi Etoh, Manabu Miura
  • Patent number: 5319256
    Abstract: A constant potential generating semiconductor device includes: an output circuit having a first channel type first transistor and a second channel type second transistor serially connected between a first power source and a second power source V.sub.
    Type: Grant
    Filed: April 29, 1992
    Date of Patent: June 7, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Koyanagi, Tsuyoshi Etoh