Abstract: A semiconductor storage device includes a memory cell array and a peripheral circuit disposed at least partially below the memory cell array. The peripheral circuit includes an RC circuit in which a resistive portion and a capacitive portion are electrically connected to each other in series. The resistive portion includes first and second lower conductors at a level that is below the memory cell array, an upper conductor at a level that is above the memory cell array, a first contact that connects the first lower conductor to the upper conductor, and a second contact that connects the upper conductor to the second lower conductor. The first lower conductor, the first contact, the upper conductor, the second contact, and the second lower conductor are electrically connected in series in this order and the first lower conductor is closest to the capacitive portion.

Abstract: According to one embodiment, a semiconductor memory device includes a core section, a corner area adjacent section, a first circuit block and a second circuit block, and multiple wiring layers. The corner area adjacent section is arranged adjacently to a corner area positioned in a corner of the core section adjacently to the sense amplifier and the row decoder. The multiple wiring layers are provided in each of the first circuit block and the second circuit block, wherein a first wire in one of the multiple wiring layers in the first circuit block is arranged parallel to a second wire included in a wiring layer in the second circuit block which is the same as the wiring layer of the first wire.

Abstract: According to one embodiment, a semiconductor memory device includes a core section, a corner area adjacent section, a first circuit block and a second circuit block, and multiple wiring layers. The corner area adjacent section is arranged adjacently to a corner area positioned in a corner of the core section adjacently to the sense amplifier and the row decoder. The multiple wiring layers are provided in each of the first circuit block and the second circuit block, wherein a first wire in one of the multiple wiring layers in the first circuit block is arranged parallel to a second wire included in a wiring layer in the second circuit block which is the same as the wiring layer of the first wire.