Patents by Inventor Tsuyoshi Hamatani
Tsuyoshi Hamatani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7777304Abstract: A seal ring is continuously formed along a boundary between a semiconductor element region and a scribe grid region, auxiliary parts are intermittently arranged along the seal ring, and the seal ring is constituted by a metal layer.Type: GrantFiled: August 3, 2006Date of Patent: August 17, 2010Assignee: Panasonic CorporationInventors: Tsuyoshi Hamatani, Yukitoshi Ota
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Patent number: 7622792Abstract: A conductive region electrically connected to a buffer coat film is formed on at least one corner of a semiconductor substrate, so that electricity charged on a package seal resin or a surface of the buffer coat film is allowed to flow toward the conductive region through a conductive path. Thus, density of the electricity charged on the package seal resin or the surface of the buffer coat film is lowered, and electric discharge can be suppressed. Since the electric discharge is suppressed, no high voltage is applied to an external input/output terminal. As a result, it is possible to prevent a circuit metal wire connected to an integrated circuit from being fused and an interlayer insulating film from being damaged.Type: GrantFiled: December 8, 2006Date of Patent: November 24, 2009Assignee: Panasonic CorporationInventors: Kazumi Watase, Tsuyoshi Hamatani
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Publication number: 20090184428Abstract: A semiconductor substrate, an interwiring insulating film formed on the semiconductor substrate, a first protective film formed on the interwiring insulating film having an opening and a pad metal formed on the opening are provided. A groove is formed in a portion corresponding to a peripheral portion of the pad metal, and the groove is covered with the pad metal. Thus, without decreasing bonding properties, insulation between pads can be maintained as well as cracks in a protective film around pads can be prevented.Type: ApplicationFiled: January 7, 2009Publication date: July 23, 2009Applicant: PANASONIC CORPORATIONInventor: Tsuyoshi HAMATANI
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Patent number: 7391114Abstract: A pad section serving as an electrode for external connection of a semiconductor device includes a first pad metal (61) formed in the top layer, a second pad metal (62) formed under the first pad metal (61) via an interlayer insulating film (71), and vias (63) which penetrate the interlayer insulating film (71) and electrically connect the first pad metal (61) and the second pad metal (62). The first pad metal (61) and the second pad metal (62) have edges displaced from each other so as not to be aligned with each other along the thickness direction of each layer. Thus, it is possible to reduce stress occurring on an edge of the second pad metal (62), thereby reducing damage on the interlayer insulating film (71) and so on.Type: GrantFiled: February 1, 2005Date of Patent: June 24, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tadaaki Mimura, Tsuyoshi Hamatani, Atuhito Mizutani, Kenji Ueda
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Patent number: 7309624Abstract: Disclosed is a semiconductor device which comprises a semiconductor element having a plurality of electrodes, a plurality of external electrodes disposed around the periphery of the semiconductor element, a fine wire electrically connected between at least one of surfaces of each of the plural external electrodes and at least one of the plural electrodes of the semiconductor element, and an encapsulating resin which encapsulates the semiconductor element, the plural external electrodes, and the fine wires and whose external shape is a rectangular parallelepiped, wherein a bottom surface of the semiconductor element and a bottom surface of each of the plural external electrode are exposed from a bottom surface of the encapsulating resin and a top surface of the semiconductor element and a top surface of each of the plural external electrode are located substantially coplanar with each other.Type: GrantFiled: July 12, 2006Date of Patent: December 18, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroaki Fujimoto, Tsuyoshi Hamatani, Toru Nomura
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Publication number: 20070138638Abstract: In a semiconductor device having a multilayer interconnection structure, wires are formed by a damascene process, at least part of electrode pads includes a first conductive layer having a region provided for an electrical connection with an external unit. Herein, the first conductive layer is formed on a passivation film that is formed a semiconductor substrate and is indispensable for the multilayer interconnection structure.Type: ApplicationFiled: November 9, 2006Publication date: June 21, 2007Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Yukitoshi Ota, Noriyuki Nagai, Tsuyoshi Hamatani
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Publication number: 20070132096Abstract: A conductive region electrically connected to a buffer coat film is formed on at least one corner of a semiconductor substrate, so that electricity charged on a package seal resin or a surface of the buffer coat film is allowed to flow toward the conductive region through a conductive path. Thus, density of the electricity charged on the package seal resin or the surface of the buffer coat film is lowered, and electric discharge can be suppressed. Since the electric discharge is suppressed, no high voltage is applied to an external input/output terminal. As a result, it is possible to prevent a circuit metal wire connected to an integrated circuit from being fused and an interlayer insulating film from being damaged.Type: ApplicationFiled: December 8, 2006Publication date: June 14, 2007Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Kazumi Watase, Tsuyoshi Hamatani
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Patent number: 7202565Abstract: A semiconductor device includes: multiple kinds of interlayer insulating films formed on a semiconductor substrate and having different elastic moduli, respectively; a metal pad arranged on said multiple kinds of interlayer insulating films; the interlayer insulating film of a low elastic modulus having the lowest elastic modulus and having an opening located under the metal pad, the interlayer insulating film of a not-low elastic modulus having the elastic modulus larger than the elastic modulus of the interlayer insulating film of the low elastic modulus, being layered in contact with the interlayer insulating film of the low elastic modulus, and continuously extending over the opening and a region surrounding the opening and a metal interconnection layer arranged under the metal pad, filling the opening in the interlayer insulating film of the low elastic modulus, and being in contact with the interlayer insulating film of the not-low elastic modulus.Type: GrantFiled: September 3, 2004Date of Patent: April 10, 2007Assignees: Renesas Technology Corp., Matsushita Electric Industrial Co., Ltd.Inventors: Masazumi Matsuura, Hiroshi Horibe, Susumu Matsumoto, Tsuyoshi Hamatani
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Publication number: 20070029641Abstract: A seal ring is continuously formed along a boundary between a semiconductor element region and a scribe grid region, auxiliary parts are intermittently arranged along the seal ring, and the seal ring is constituted by a metal layer.Type: ApplicationFiled: August 3, 2006Publication date: February 8, 2007Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Tsuyoshi Hamatani, Yukitoshi Ota
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Publication number: 20070023927Abstract: When an interlayer film (22) is formed to have a large thickness and an electrode pad (11) is partly or wholly led out from an active region (16), an I/O region (15) can be reduced in area. Thus, it is possible to reduce an area of a semiconductor device.Type: ApplicationFiled: July 17, 2006Publication date: February 1, 2007Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Noriyuki Nagai, Tsuyoshi Hamatani, Tadaaki Mimura
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Publication number: 20060252183Abstract: Disclosed is a semiconductor device which comprises a semiconductor element having a plurality of electrodes, a plurality of external electrodes disposed around the periphery of the semiconductor element, a fine wire electrically connected between at least one of surfaces of each of the plural external electrodes and at least one of the plural electrodes of the semiconductor element, and an encapsulating resin which encapsulates the semiconductor element, the plural external electrodes, and the fine wires and whose external shape is a rectangular parallelepiped, wherein a bottom surface of the semiconductor element and a bottom surface of each of the plural external electrode are exposed from a bottom surface of the encapsulating resin and a top surface of the semiconductor element and a top surface of each of the plural external electrode are located substantially coplanar with each other.Type: ApplicationFiled: July 12, 2006Publication date: November 9, 2006Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Hiroaki Fujimoto, Tsuyoshi Hamatani, Toru Nomura
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Patent number: 7125751Abstract: Disclosed is a semiconductor device which comprises a semiconductor element having a plurality of electrodes, a plurality of external electrodes disposed around the periphery of the semiconductor element, a fine wire electrically connected between at least one of surfaces of each of the plural external electrodes and at least one of the plural electrodes of the semiconductor element, and an encapsulating resin which encapsulates the semiconductor element, the plural external electrodes, and the fine wires and whose external shape is a rectangular parallelepiped, wherein a bottom surface of the semiconductor element and a bottom surface of each of the plural external electrode are exposed from a bottom surface of the encapsulating resin and a top surface of the semiconductor element and a top surface of each of the plural external electrode are located substantially coplanar with each other.Type: GrantFiled: January 26, 2005Date of Patent: October 24, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroaki Fujimoto, Tsuyoshi Hamatani, Toru Nomura
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Publication number: 20050173801Abstract: A pad section serving as an electrode for external connection of a semiconductor device includes a first pad metal (61) formed in the top layer, a second pad metal (62) formed under the first pad metal (61) via an interlayer insulating film (71), and vias (63) which penetrate the interlayer insulating film (71) and electrically connect the first pad metal (61) and the second pad metal (62). The first pad metal (61) and the second pad metal (62) have edges displaced from each other so as not to be aligned with each other along the thickness direction of each layer. Thus, it is possible to reduce stress occurring on an edge of the second pad metal (62), thereby reducing damage on the interlayer insulating film (71) and so on.Type: ApplicationFiled: February 1, 2005Publication date: August 11, 2005Applicant: Matsushita Elec. Ind. Co. Ltd.Inventors: Tadaaki Mimura, Tsuyoshi Hamatani, Atuhito Mizutani, Kenji Ueda
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Publication number: 20050133892Abstract: Disclosed is a semiconductor device which comprises a semiconductor element having a plurality of electrodes, a plurality of external electrodes disposed around the periphery of the semiconductor element, a fine wire electrically connected between at least one of surfaces of each of the plural external electrodes and at least one of the plural electrodes of the semiconductor element, and an encapsulating resin which encapsulates the semiconductor element, the plural external electrodes, and the fine wires and whose external shape is a rectangular parallelepiped, wherein a bottom surface of the semiconductor element and a bottom surface of each of the plural external electrode are exposed from a bottom surface of the encapsulating resin and a top surface of the semiconductor element and a top surface of each of the plural external electrode are located substantially coplanar with each other.Type: ApplicationFiled: January 26, 2005Publication date: June 23, 2005Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroaki Fujimoto, Tsuyoshi Hamatani, Toru Nomura
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Publication number: 20050054188Abstract: A semiconductor device includes: multiple kinds of interlayer insulating films formed on a semiconductor substrate and having different elastic moduli, respectively; a metal pad arranged on said multiple kinds of interlayer insulating films; the interlayer insulating film of a low elastic modulus having the lowest elastic modulus and having an opening located under the metal pad, the interlayer insulating film of a not-low elastic modulus having the elastic modulus larger than the elastic modulus of the interlayer insulating film of the low elastic modulus, being layered in contact with the interlayer insulating film of the low elastic modulus, and continuously extending over the opening and a region surrounding the opening and a metal interconnection layer arranged under the metal pad, filling the opening in the interlayer insulating film of the low elastic modulus, and being in contact with the interlayer insulating film of the not-low elastic modulus.Type: ApplicationFiled: September 3, 2004Publication date: March 10, 2005Inventors: Masazumi Matsuura, Hiroshi Horibe, Susumu Matsumoto, Tsuyoshi Hamatani
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Patent number: 6856026Abstract: A semiconductor chip which does not increase the thickness or the board area of a semiconductor device wherein semiconductor chips are layered and does not increase the wire length between the semiconductor chips even in the case that a plurality of semiconductor chips are layered on a wiring board and a process thereof, as well as a semiconductor device, and the like, are provided.Type: GrantFiled: July 11, 2003Date of Patent: February 15, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yuichiro Yamada, Tsuyoshi Hamatani
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Patent number: 6835600Abstract: A lead frame includes: an outer frame section; a plurality of chip mounting sections which are supported by the outer frame section and on which a plurality of semiconductor chips are mounted; lead sections surrounding the chip mounting sections; connecting sections for connecting and supporting the lead sections and the outer frame section with each other; and an encapsulation region in which the chip mounting sections are encapsulated together in an encapsulation resin. An opening is provided in a plurality of regions of the outer frame section that are each located outside the encapsulation region and along the extension of one of the connecting sections.Type: GrantFiled: May 16, 2003Date of Patent: December 28, 2004Assignee: Matsushita Electric Industrial Co., LTDInventors: Masaki Utsumi, Masashi Funakoshi, Tsuyoshi Hamatani, Takeshi Morikawa, Yukio Nakabayashi
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Patent number: 6693358Abstract: A semiconductor chip which does not increase the thickness or the board area of a semiconductor device wherein semiconductor chips are layered and does not increase the wire length between the semiconductor chips even in the case that a plurality of semiconductor chips are layered on a wiring board and a process thereof, as well as a semiconductor device, and the like, are provided.Type: GrantFiled: October 10, 2001Date of Patent: February 17, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yuichiro Yamada, Tsuyoshi Hamatani
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Publication number: 20040017012Abstract: A semiconductor chip which does not increase the thickness or the board area of a semiconductor device wherein semiconductor chips are layered and does not increase the wire length between the semiconductor chips even in the case that a plurality of semiconductor chips are layered on a wiring board and a process thereof, as well as a semiconductor device, and the like, are provided.Type: ApplicationFiled: July 11, 2003Publication date: January 29, 2004Inventors: Yuichiro Yamada, Tsuyoshi Hamatani
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Publication number: 20030203541Abstract: A lead frame includes: an outer frame section; a plurality of chip mounting sections which are supported by the outer frame section and on which a plurality of semiconductor chips are mounted; lead sections surrounding the chip mounting sections; connecting sections for connecting and supporting the lead sections and the outer frame section with each other; and an encapsulation region in which the chip mounting sections are encapsulated together in an encapsulation resin. An opening is provided in a plurality of regions of the outer frame section that are each located outside the encapsulation region and along the extension of one of the connecting sections.Type: ApplicationFiled: May 16, 2003Publication date: October 30, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Masaki Utsumi, Masashi Funakoshi, Tsuyoshi Hamatani, Takeshi Morikawa, Yukio Nakabayashi