Abstract: According to one embodiment, a method of controlling a MEMS variable capacitor includes first and second electrodes, and having a capacitance varying according to a voltage applied between the first and second electrodes, the method includes applying a voltage between the first and second electrodes, evaluating whether the capacitance of the MEMS variable capacitor satisfies a predetermined condition while the voltage is being applied between the first and second electrodes, and determining that the voltage applied between the first and second electrodes is a voltage which should be applied therebetween, on a condition that the capacitance of the MEMS variable capacitor is evaluated as satisfying the predetermined condition.

Abstract: According to one embodiment, an electronic device includes a MEMS element formed on an underlying region, and a stack film covering the MEMS element and forming a cavity part inside, wherein the stack film includes a first layer having a hole, a second layer provided on the first layer and covering the hole, a third layer provided on the second layer and formed of an oxide, and a fourth layer provided on the third layer and formed of a nitride.

Abstract: According to one embodiment, a MEMS device is disclosed. The device includes a substrate, a MEMS element as a first component provided on the substrate, a first film having a plurality of through holes. The first film and the substrate are configured to form a cavity accommodating the MEMS element. The device further includes a second film provided on the first film, a second component provided on the substrate and disposed outside of the cavity, and a film provided on the substrate and disposed outside of the cavity, and configured to surround the second component.

Abstract: According to one embodiment, the semiconductor device with element isolation by DTI has a layer of the first electroconductive type formed on a substrate. The semiconductor layer of the second electroconductive type is formed on the embedding layer. The first DTI has the following structure: a trench is formed from the surface of the semiconductor layer through the first layer into the substrate and surrounds the semiconductor layer, and an insulator is formed in the trench. The second DTI is formed around the periphery of the semiconductor layer. The first electrode is connected to the first region of the semiconductor layer divided by the first DTI. The second electrode is connected to the second region of the semiconductor layer divided as mentioned previously. The first region and the second region form electrode plates and the first DTI forms the dielectric, to thereby form a capacitor.

Abstract: According to one embodiment, the semiconductor device with element isolation by DTI has a layer of the first electroconductive type formed on a substrate. The semiconductor layer of the second electroconductive type is formed on the embedding layer. The first DTI has the following structure: a trench is formed from the surface of the semiconductor layer through the first layer into the substrate and surrounds the semiconductor layer, and an insulator is formed in the trench. The second DTI is formed around the periphery of the semiconductor layer. The first electrode is connected to the first region of the semiconductor layer divided by the first DTI. The second electrode is connected to the second region of the semiconductor layer divided as mentioned previously. The first region and the second region form electrode plates and the first DTI forms the dielectric, to thereby form a capacitor.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate with a p-type conductivity, a buried layer with an n-type conductivity provided on the semiconductor substrate, a back gate layer with a p-type conductivity provided on the buried layer, a drain layer with an n-type conductivity provided on the back gate layer, a source layer with an n-type conductivity provided spaced from the drain layer, a gate electrode provided in a region immediately above a portion of the back gate layer between the drain layer and the source layer, and a drain electrode in contact with a part of an upper surface of the drain layer. A thickness of the drain layer in a region immediately below a contact surface between the drain layer and the drain electrode is half a total thickness of the back gate and drain layers in the region.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate with a p-type conductivity, a buried layer with an n-type conductivity provided on the semiconductor substrate, a back gate layer with a p-type conductivity provided on the buried layer, a drain layer with an n-type conductivity provided on the back gate layer, a source layer with an n-type conductivity provided spaced from the drain layer, a gate electrode provided in a region immediately above a portion of the back gate layer between the drain layer and the source layer, and a drain electrode in contact with a part of an upper surface of the drain layer. A thickness of the drain layer in a region immediately below a contact surface between the drain layer and the drain electrode is half a total thickness of the back gate and drain layers in the region.

Abstract: According to one embodiment, there is provided a method of manufacturing a semiconductor device having a buffer circuit. In the method, a plurality of semiconductor elements is formed on a semiconductor substrate. The plurality of semiconductor elements are connected in parallel to each other in the buffer circuit. In the method, driving forces of the formed semiconductor elements is evaluated. In the method, one mask is selected from a plurality of masks based on the evaluating. The plurality of masks are formed in advance to have different wiring mask patterns to cause the numbers of semiconductor elements connected in parallel with each other among the plurality of semiconductor elements of the buffer circuit to be different from each other. In the method, a wiring pattern corresponding to the wiring mask pattern is formed by using the selected one mask.

Abstract: According to one embodiment, there is provided a method of manufacturing a semiconductor device having a buffer circuit. In the method, a plurality of semiconductor elements is formed on a semiconductor substrate. The plurality of semiconductor elements are connected in parallel to each other in the buffer circuit. In the method, driving forces of the formed semiconductor elements is evaluated. In the method, one mask is selected from a plurality of masks based on the evaluating. The plurality of masks are formed in advance to have different wiring mask patterns to cause the numbers of semiconductor elements connected in parallel with each other among the plurality of semiconductor elements of the buffer circuit to be different from each other. In the method, a wiring pattern corresponding to the wiring mask pattern is formed by using the selected one mask.