Patents by Inventor Tsuyoshi Horikawa
Tsuyoshi Horikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10340399Abstract: Provided is an optical device in which an Si cap layer is provided on a Ge layer, and which is capable of effectively reducing dark current, while having a good effect on prevention of production line contamination by Ge. One embodiment of the optical device according to the present invention is provided with: a semiconductor layer which contains Ge and has a (001) surface and a facet surface between the (001) surface and a (110) surface; and a cap layer which is formed from Si, and which is formed on the (001) surface and the facet surface of the semiconductor layer. The ratio of the film thickness of the cap layer on the facet surface to the film thickness of the cap layer on the (001) surface is 0.4 or more; and the film thickness of the cap layer on the (001) surface is from 9 nm to 30 nm (inclusive).Type: GrantFiled: July 28, 2016Date of Patent: July 2, 2019Assignee: PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATIONInventors: Shigekazu Okumura, Tohru Mogami, Keizo Kinoshita, Tsuyoshi Horikawa, Junichi Fujikata
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Patent number: 10247882Abstract: Provided is an optical waveguide circuit avoiding the difficulty of the property compensation based on temperature control, compensated with respect to the property variations due to fabrication error, particularly paid attention in a silicon waveguide, and being low in power consumption and high in performances. The optical waveguide circuit includes a silicon (Si) substrate, a buried oxide film (BOX) layer formed on the Si substrate, and an SOI (Silicon on Insulator) layer, formed on the BOX layer, including an optical element utilizing the SOI layer as a main optical transmission medium. At least part of a waveguide of the optical element includes uniformly distributed and thermally unstable crystal defects.Type: GrantFiled: August 31, 2017Date of Patent: April 2, 2019Assignees: NEC CORPORATION, PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATIONInventors: Tsuyoshi Horikawa, Tohru Mogami, Keizo Kinoshita
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Publication number: 20190006532Abstract: Provided is an optical device in which an Si cap layer is provided on a Ge layer, and which is capable of effectively reducing dark current, while having a good effect on prevention of production line contamination by Ge. One embodiment of the optical device according to the present invention is provided with: a semiconductor layer which contains Ge and has a (001) surface and a facet surface between the (001) surface and a (110) surface; and a cap layer which is formed from Si, and which is formed on the (001) surface and the facet surface of the semiconductor layer. The ratio of the film thickness of the cap layer on the facet surface to the film thickness of the cap layer on the (001) surface is 0.4 or more; and the film thickness of the cap layer on the (001) surface is from 9 nm to 30 nm (inclusive).Type: ApplicationFiled: July 28, 2016Publication date: January 3, 2019Applicant: PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATIONInventors: Shigekazu Okumura, Tohru Mogami, Keizo Kinoshita, Tsuyoshi Horikawa, Junichi Fujikata
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Patent number: 10162110Abstract: A semiconductor device is provided with an insulating layer formed on a base substrate, an optical waveguide composed of a semiconductor layer formed on the insulating layer, and an insulating film formed along an upper surface of the insulating layer and a front surface of the optical waveguide. A peripheral edge portion of a lower surface of the optical waveguide is separated from the insulating layer, and the insulating film is buried between the peripheral edge portion and the insulating layer.Type: GrantFiled: August 22, 2016Date of Patent: December 25, 2018Assignees: RENESAS ELECTRONICS CORPORATION, PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATIONInventors: Tatsuya Usami, Keiji Sakamoto, Yoshiaki Yamamoto, Shinichi Watanuki, Masaru Wakabayashi, Tohru Mogami, Tsuyoshi Horikawa, Keizo Kinoshita
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Publication number: 20180284559Abstract: Provided is a silicon-based electro-optic modulator that exhibits an improved carrier plasma effect which is capable of realizing a low current density, low power consumption, a high modulation rate, low-voltage driving and high-speed modulation in a sub-micron region. The electro-optic modulator includes a waveguide structure including an Si or SiGe crystal. The electric field direction of light that propagates inside the waveguide structure is set to be approximately parallel with the <110> direction of the Si or SiGe crystal.Type: ApplicationFiled: March 29, 2018Publication date: October 4, 2018Applicants: NEC CORPORATION, PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIAT IONInventors: Junichi FUJIKATA, Tohru MOGAMI, Takahiro NAKAMURA, Tsuyoshi HORIKAWA
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Patent number: 10078182Abstract: When an optical waveguide is formed, an area of an opening of a resist mask is equal to an area of a semiconductor layer for a dummy pattern exposed from the resist mask, and the semiconductor layer for the dummy pattern exposed from the resist mask has a uniform thickness in a region in which the dummy pattern is formed. As a result, an effective pattern density does not change in etching the semiconductor layer for the dummy pattern, and accordingly, it is possible to form a rib-shaped optical waveguide having desired dimensions and a desired shape.Type: GrantFiled: August 22, 2016Date of Patent: September 18, 2018Assignees: RENESAS ELECTRONICS CORPORATION, PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATIONInventors: Shinichi Watanuki, Akira Mitsuiki, Atsuro Inada, Tohru Mogami, Tsuyoshi Horikawa, Keizo Kinoshita
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Patent number: 9985149Abstract: A performance of a semiconductor device is improved. In a method of manufacturing a semiconductor device, a first semiconductor portion and a second semiconductor portion made of silicon are formed on a base body via an insulation layer, and a third semiconductor portion including a semiconductor layer made of germanium is formed on the second semiconductor portion. Next, an insulation film is formed above the first semiconductor portion, an opening portion reaching the first semiconductor portion from an upper surface of the insulation film is formed, and a metal silicide layer is formed on a part of an upper surface of the first semiconductor portion exposed to the opening portion.Type: GrantFiled: August 23, 2016Date of Patent: May 29, 2018Assignees: RENESAS ELECTRONICS CORPORATION, PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATIONInventors: Tatsuya Usami, Yoshiaki Yamamoto, Keiji Sakamoto, Tohru Mogami, Tsuyoshi Horikawa, Keizo Kinoshita
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Publication number: 20180067260Abstract: Provided is an optical waveguide circuit avoiding the difficulty of the property compensation based on temperature control, compensated with respect to the property variations due to fabrication error, particularly paid attention in a silicon waveguide, and being low in power consumption and high in performances. The optical waveguide circuit includes a silicon (Si) substrate, a buried oxide film (BOX) layer formed on the Si substrate, and an SOI (Silicon on Insulator) layer, formed on the BOX layer, including an optical element utilizing the SOI layer as a main optical transmission medium. At least part of a waveguide of the optical element includes uniformly distributed and thermally unstable crystal defects.Type: ApplicationFiled: August 31, 2017Publication date: March 8, 2018Inventors: Tsuyoshi HORIKAWA, Tohru MOGAMI, Keizo KINOSHITA
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Patent number: 9869815Abstract: An optical device includes an optical waveguide provided on a principal surface of a substrate. The optical waveguide includes a core and a cladding provided around the core. The cladding is configured by a substance having a refractive index smaller than 71.4% of the refractive index of the core. The core has constituent atoms substantially forming a diamond lattice structure. The optical waveguide has a light input/output part through which a light beam is input and/or output. The light input/output part decreases stepwise in thickness towards an output end while tapering down in its width. The core is provided in the light input/output part to have a (111) plane or an equivalent plane to the (111) plane exposed on a face of a riser of the stepwise thickness of the light input/output part.Type: GrantFiled: April 8, 2016Date of Patent: January 16, 2018Assignees: Oki Electric Industry Co., Ltd., National Institute of Advanced Industrial Science and Technology, Photonics Electronics Technology Research AssociationInventors: Hideki Ono, Tsuyoshi Horikawa, Naoki Hirayama
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Publication number: 20170068047Abstract: A semiconductor device is provided with an insulating layer formed on a base substrate, an optical waveguide composed of a semiconductor layer formed on the insulating layer, and an insulating film formed along an upper surface of the insulating layer and a front surface of the optical waveguide. A peripheral edge portion of a lower surface of the optical waveguide is separated from the insulating layer, and the insulating film is buried between the peripheral edge portion and the insulating layer.Type: ApplicationFiled: August 22, 2016Publication date: March 9, 2017Inventors: TATSUYA USAMI, KEIJI SAKAMOTO, YOSHIAKI YAMAMOTO, SHINICHI WATANUKI, MASARU WAKABAYASHI, TOHRU MOGAMI, TSUYOSHI HORIKAWA, KEIZO KINOSHITA
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Publication number: 20170069769Abstract: A performance of a semiconductor device is improved. In a method of manufacturing a semiconductor device, a first semiconductor portion and a second semiconductor portion made of silicon are formed on a base body via an insulation layer, and a third semiconductor portion including a semiconductor layer made of germanium is formed on the second semiconductor portion. Next, an insulation film is formed above the first semiconductor portion, an opening portion reaching the first semiconductor portion from an upper surface of the insulation film is formed, and a metal silicide layer is formed on a part of an upper surface of the first semiconductor portion exposed to the opening portion.Type: ApplicationFiled: August 23, 2016Publication date: March 9, 2017Inventors: Tatsuya USAMI, Yoshiaki YAMAMOTO, Keiji SAKAMOTO, Tohru MOGAMI, Tsuyoshi HORIKAWA, Keizo KINOSHITA
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Publication number: 20170068051Abstract: When an optical waveguide is formed, an area of an opening of a resist mask is equal to an area of a semiconductor layer for a dummy pattern exposed from the resist mask, and the semiconductor layer for the dummy pattern exposed from the resist mask has a uniform thickness in a region in which the dummy pattern is formed. As a result, an effective pattern density does not change in etching the semiconductor layer for the dummy pattern, and accordingly, it is possible to form a rib-shaped optical waveguide having desired dimensions and a desired shape.Type: ApplicationFiled: August 22, 2016Publication date: March 9, 2017Inventors: Shinichi WATANUKI, Akira MITSUIKl, Atsuro INADA, Tohru MOGAMI, Tsuyoshi HORIKAWA, Keizo KINOSHITA
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Publication number: 20160223748Abstract: An optical device includes an optical waveguide provided on a principal surface of a substrate. The optical waveguide includes a core and a cladding provided around the core. The cladding is configured by a substance having a refractive index smaller than 71.4% of the refractive index of the core. The core has constituent atoms substantially forming a diamond lattice structure. The optical waveguide has a light input/output part through which a light beam is input and/or output. The light input/output part decreases stepwise in thickness towards an output end while tapering down in its width. The core is provided in the light input/output part to have a (111) plane or an equivalent plane to the (111) plane exposed on a face of a riser of the stepwise thickness of the light input/output part.Type: ApplicationFiled: April 8, 2016Publication date: August 4, 2016Applicants: Oki Electric Industry Co., Ltd., National Institute Of Advanced Industrial Science And Technology, Photonics Electronics Technology Research AssociationInventors: Hideki ONO, Tsuyoshi HORIKAWA, Naoki HIRAYAMA
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Patent number: 9335475Abstract: In a method of manufacturing an optical device including an optical waveguide having a core, a cladding and a light input/output part through which a light beam is input or output, a substrate is prepared which is provided with a uniform thickness of single-crystalline film having its constituent atoms forming a diamond lattice structure and its surface being neither the (111) plane nor its equivalent planes. In the single-crystalline film, a precursor structure is formed which has a precursor of light input/output part. A mask is formed such as to expose the precursor with the remaining part covered. The structure is immersed into an alkaline solution for wet etching with the (111) planes used as etch-stop planes.Type: GrantFiled: September 10, 2014Date of Patent: May 10, 2016Assignees: OKI ELECTRIC INDUSTRY CO., LTD., NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATIONInventors: Hideki Ono, Tsuyoshi Horikawa, Naoki Hirayama
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Publication number: 20150086153Abstract: In a method of manufacturing an optical device including an optical waveguide having a core, a cladding and a light input/output part through which a light beam is input or output, a substrate is prepared which is provided with a uniform thickness of single-crystalline film having its constituent atoms forming a diamond lattice structure and its surface being neither the (111) plane nor its equivalent planes. In the single-crystalline film, a precursor structure is formed which has a precursor of light input/output part. A mask is formed such as to expose the precursor with the remaining part covered. The structure is immersed into an alkaline solution for wet etching with the (111) planes used as etch-stop planes.Type: ApplicationFiled: September 10, 2014Publication date: March 26, 2015Applicants: OKI ELECTRIC INDUSTRY CO., LTD., National Institute of Advanced Industrial Science and Technology, Photonics Electronics Technology Research AssociationInventors: Hideki ONO, Tsuyoshi HORIKAWA, Naoki HIRAYAMA
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Patent number: 8351805Abstract: A power saving processing apparatus that includes a processing unit, an output unit and a transition unit is provided. The processing unit is configured to transition from a first state where power is supplied to a second state where power supply is restricted, executes a first process required for such transition before transition from the first state to the second state, and executes a second process to output a first signal after executing the first process. The output unit outputs a second signal after receiving the first signal output from the processing unit, and outputs the second signal when not receiving the first signal output from the processing unit within a predetermined time period after a predetermined time after the first process starts. The transition unit transitions the processing unit to the second state after receiving the second signal output from the output unit.Type: GrantFiled: February 24, 2010Date of Patent: January 8, 2013Assignee: Fuji Xerox Co., Ltd.Inventors: Tsutomu Nakaminato, Tsuyoshi Horikawa
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Publication number: 20110076038Abstract: A power saving processing apparatus that includes a processing unit, an output unit and a transition unit is provided. The processing unit is configured to transition from a first state where power is supplied to a second state where power supply is restricted, executes a first process required for such transition before transition from the first state to the second state, and executes a second process to output a first signal after executing the first process. The output unit outputs a second signal after receiving the first signal output from the processing unit, and outputs the second signal when not receiving the first signal output from the processing unit within a predetermined time period after a predetermined time after the first process starts. The transition unit transitions the processing unit to the second state after receiving the second signal output from the output unit.Type: ApplicationFiled: February 24, 2010Publication date: March 31, 2011Applicant: Fuji Xerox Co., Ltd.Inventors: Tsutomu NAKAMINATO, Tsuyoshi Horikawa
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Patent number: 7397094Abstract: To provide a semiconductor device that enables to suppress a defect density of a gate insulating film of an MISFET, gain a sufficient electric characteristic thereof, and make an Equivalent Oxide Thickness (EOT) of the gate insulating film 1.0 nm or less. The MISFETs are formed to have the gate insulating film formed on a main surface of a silicon substrate, and a gate electrode formed on the gate insulating film, wherein the gate insulating film includes a metal silicate layer formed by a metal oxide layer and a silicon oxide layer and the metal silicate layer is formed so as to have concentration gradients of metal and silicon from a silicon substrate side toward a gate electrode side.Type: GrantFiled: April 26, 2005Date of Patent: July 8, 2008Assignees: Renesas Technology Corporation, National Institute of Advanced Industrial Science and Technology, Rohm Co., Ltd., Horiba., Ltd.Inventors: Toshihide Nabatame, Akira Toriumi, Tsuyoshi Horikawa, Kunihiko Iwamoto, Koji Tominaga
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Publication number: 20050236675Abstract: To provide a semiconductor device that enables to suppress a defect density of a gate insulating film of an MISFET, gain a sufficient electric characteristic thereof, and make an Equivalent Oxide Thickness (EOT) of the gate insulating film 1.0 nm or less. The MISFETs are formed to have the gate insulating film formed on a main surface of a silicon substrate, and a gate electrode formed on the gate insulating film, wherein the gate insulating film includes a metal silicate layer formed by a metal oxide layer and a silicon oxide layer and the metal silicate layer is formed so as to have concentration gradients of metal and silicon from a silicon substrate side toward a gate electrode side.Type: ApplicationFiled: April 26, 2005Publication date: October 27, 2005Inventors: Toshihide Nabatame, Akira Toriumi, Tsuyoshi Horikawa, Kunihiko Iwamoto, Koji Tominaga
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Patent number: 6780476Abstract: An object of the present invention is to provide a liquid material for chemical vapor deposition (CVD), a method of forming a film by CVD and a CVD apparatus, capable of achieving film formation of a silicate compound of good quality. A liquid material for CVD includes an organometallic compound, a siloxane compound and an organic solvent for dissolving the organometallic compound and the siloxane compound. If the organometallic compound includes an alcoxyl group (e.g., tertialy-butoxyl group) having a larger number of carbon atoms than a propoxyl group or a &bgr;-diketone group (e.g., 2,2,6,6-tetramethyl-3,5-heptanedionate group), the stability in film formation is improved. As the organic solvent, diethyl ether, tetrahydrofuran, nor-octane, iso-octane and the like may be employed. As the siloxane compound, tri-metoxy-silane having a high degree of solubility in a nonsolar solvent and hexa-methyl-di-siloxane and octa-methyl-cycro-tetra-siloxane both having solubility in a polar solvent may be employed.Type: GrantFiled: August 1, 2002Date of Patent: August 24, 2004Assignee: Renesas Technology Corp.Inventor: Tsuyoshi Horikawa