Patents by Inventor Tsuyoshi Hosono

Tsuyoshi Hosono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10825808
    Abstract: The semiconductor device includes a semiconductor layer having a main surface, a first semiconductor region of a first conductivity type formed in a surface layer portion of the main surface of the semiconductor layer, a second semiconductor region of a second conductivity type formed in a surface layer portion of the first semiconductor region and forming a zener diode with the first semiconductor region, a third semiconductor region of the first conductivity type formed in the surface layer portion of the first semiconductor region separated from the second semiconductor region, a fourth semiconductor region of the second conductivity type formed in a region between the second semiconductor region and the third semiconductor region in the surface layer portion of the first semiconductor region and having a second conductivity type impurity concentration less than a second conductivity type impurity concentration of the second semiconductor region, and an insulating layer formed on the main surface of the se
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: November 3, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Toshiyuki Kanaya, Tsuyoshi Hosono
  • Patent number: 10593685
    Abstract: A semiconductor device includes a semiconductor layer having a main surface, a gate insulating film including a thin film portion forming a tunnel window, a thick film portion formed around the thin film portion and having a thickness larger than a thickness of the thin film portion, and an inclined portion connecting the thin film portion and the thick film portion and inclined upward from the thin film portion toward the thick film portion, and covering the main surface of the semiconductor layer, a memory gate structure formed on the thin film portion of the gate insulating film, and a select gate structure formed on the thick film portion of the gate insulating film.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: March 17, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Toshiyuki Kanaya, Tsuyoshi Hosono
  • Publication number: 20190109148
    Abstract: A semiconductor device includes a semiconductor layer having a main surface, a gate insulating film including a thin film portion forming a tunnel window, a thick film portion formed around the thin film portion and having a thickness larger than a thickness of the thin film portion, and an inclined portion connecting the thin film portion and the thick film portion and inclined upward from the thin film portion toward the thick film portion, and covering the main surface of the semiconductor layer, a memory gate structure formed on the thin film portion of the gate insulating film, and a select gate structure formed on the thick film portion of the gate insulating film.
    Type: Application
    Filed: October 10, 2018
    Publication date: April 11, 2019
    Applicant: ROHM CO., LTD.
    Inventors: Toshiyuki KANAYA, Tsuyoshi HOSONO
  • Publication number: 20190081040
    Abstract: The semiconductor device includes a semiconductor layer having a main surface, a first semiconductor region of a first conductivity type formed in a surface layer portion of the main surface of the semiconductor layer, a second semiconductor region of a second conductivity type formed in a surface layer portion of the first semiconductor region and forming a zener diode with the first semiconductor region, a third semiconductor region of the first conductivity type formed in the surface layer portion of the first semiconductor region separated from the second semiconductor region, a fourth semiconductor region of the second conductivity type formed in a region between the second semiconductor region and the third semiconductor region in the surface layer portion of the first semiconductor region and having a second conductivity type impurity concentration less than a second conductivity type impurity concentration of the second semiconductor region, and an insulating layer formed on the main surface of the se
    Type: Application
    Filed: September 11, 2018
    Publication date: March 14, 2019
    Applicant: ROHM CO., LTD.
    Inventors: Toshiyuki KANAYA, Tsuyoshi HOSONO
  • Patent number: 9171962
    Abstract: A semiconductor device includes a gate insulating film formed on the semiconductor substrate; a floating gate formed on the gate insulating film; a control gate formed on the floating gate and has a side coplanar with a side of the floating gate; a tunnel diffusion layer facing a portion of the floating gate; and a tunnel window formed in a portion of the gate insulating film between the floating gate and the tunnel diffusion layer, the tunnel window being formed to be thinner than a remaining peripheral portion of the gate insulating film.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: October 27, 2015
    Assignee: ROHM CO., LTD.
    Inventor: Tsuyoshi Hosono
  • Publication number: 20150020758
    Abstract: Provided is a shutter device having a fail-safe function to prevent occurrence of overheating even when an actuator becomes inoperable. The shutter device includes a shutter valve (11) which opens and closes an air port, a lever (14a) having one end connected to a rotating shaft (16) of the shutter valve and the other end connected to an actuator (12), and biasing means which biases the shutter valve in an opening direction. Opening/closing of the shutter valve is controlled by the actuator rotating the lever when opening of the shutter valve is between the fully-open and predetermined opening, and the shutter valve is closed by wind pressure of travelling wind when the opening of the shutter valve is between the predetermined opening and the fully-closed.
    Type: Application
    Filed: December 3, 2012
    Publication date: January 22, 2015
    Inventors: Tsuyoshi Hosono, Takahiko Kimura
  • Patent number: 8310085
    Abstract: An object of this invention is to provide an electrical junction box for a vehicle that can effectively restrain a control circuit from being subject to heat adverse effect from to a power distribution circuit, can downsize the whole structure, and can reduce the number of terminals for connecting the circuits to each other. The electrical junction box for a vehicle comprises a power distribution unit for constituting a part of the power distribution circuit, and a circuit board. A board body of the circuit board is divided into a power distribution circuit region Ap and a control circuit region Ac by a border line BL across the circuit board body. The control circuit is incorporated in the control circuit region Ac. The power distribution circuit region Ap is provided with a power distribution circuit having a current specification smaller than that of the power distribution circuit on the power distribution unit.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: November 13, 2012
    Assignee: Sumitomo Wiring Systems, Ltd.
    Inventors: Yoshiaki Sugimura, Tsuyoshi Hosono
  • Publication number: 20100231038
    Abstract: An object of this invention is to provide an electrical junction box for a vehicle that can effectively restrain a control circuit from being subject to heat adverse effect from to a power distribution circuit, can downsize the whole structure, and can reduce the number of terminals for connecting the circuits to each other. The electrical junction box for a vehicle comprises a power distribution unit for constituting a part of the power distribution circuit, and a circuit board. A board body of the circuit board is divided into a power distribution circuit region Ap and a control circuit region Ac by a border line BL across the circuit board body. The control circuit is incorporated in the control circuit region Ac. The power distribution circuit region Ap is provided with a power distribution circuit having a current specification smaller than that of the power distribution circuit on the power distribution unit.
    Type: Application
    Filed: May 27, 2008
    Publication date: September 16, 2010
    Applicant: SUMITOMO WIRING SYSTEMS, LTD.
    Inventors: Yoshiaki Sugimura, Tsuyoshi Hosono
  • Publication number: 20090100306
    Abstract: An MC 10 includes a universal asynchronous receiver transceiver UART as a communication circuit. A tester (6) includes a serial communication interface (61). By serial communication between these two, the operation of an electronic unit 1 is tested. A common output circuit (31) is provided as an output circuit of the UART 11. This common output circuit (31) is a circuit which doubles as one of output circuits of the MC 10, one end thereof is connected to a UART port and another general port of the MC 10 and the other end thereof is connected to a terminal connected to a load (7).
    Type: Application
    Filed: October 6, 2008
    Publication date: April 16, 2009
    Applicant: Sumitomo Wiring Systems, Ltd.
    Inventors: Yoshiaki Sugimura, Tsuyoshi Hosono
  • Patent number: 7385431
    Abstract: An input circuit commonly uses input ports of a microcomputer for a plurality of contact input terminals such as switches provided on the way to the ground. Transistors (Q1) to (Q8) whose bases are connected with contact input terminals (IN1) to (IN8) are provided. Groups of transistors, such as odd-numbered transistors and even-numbered transistors, are made selectable or non-selectable together by a selection output from an I/O port (P01) or (P02) of a microcomputer (12), and collector currents of a plurality of transistors (Q1, Q2; Q3, Q4; Q5, Q6; Q7, Q8) which are not simultaneously selected are converted into voltages using common resistors (R1) to (R4). These voltages then are fed to I/O ports (P1) to (P4). Accordingly, even upon a rise of a contact input from a ground potential due to the ON resistance of switches (SW1) to (SW8), the states of the contacts can be judged precisely.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: June 10, 2008
    Assignee: Sumitomo Wiring Systems, Ltd.
    Inventor: Tsuyoshi Hosono
  • Patent number: 7051615
    Abstract: The present apparatus includes an accelerator pedal 10, a pedal arm 20, a pedal shaft 30 which supports the pedal arm 20 so as to be free to swing, a return spring 40, a friction generating mechanism 50 which generates friction force corresponding to a position of the pedal arm 20, an accelerator position sensor 60 and a control segment 70 which controls an opening of a throttle valve 110 based on an output signal of the sensor 60. A play range in which a friction force equal to or larger than a specific level is not generated is set to the friction generating mechanism in the range where the pedal arm moves from a resting position by a specific amount. In the play range, an output signal of the accelerator position sensor 60 is kept constant so that the throttle valve is kept at a specific opening. In this manner, a desirable operating feeling without an unsuitable feeling with the accelerator pedal operation is obtained, and the accelerator apparatus is compact.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: May 30, 2006
    Assignee: Mikuni Corporation
    Inventors: Masato Kumamoto, Takumi Oikawa, Tsuyoshi Hosono
  • Publication number: 20060082382
    Abstract: An input circuit commonly uses input ports of a microcomputer for a plurality of contact input terminals such as switches provided on the way to the ground. Transistors (Q1) to (Q8) whose bases are connected with contact input terminals (IN1) to (IN8) are provided. Groups of transistors, such as odd-numbered transistors and even-numbered transistors, are made selectable or non-selectable together by a selection output from an I/O port (P01) or (P02) of a microcomputer (12), and collector currents of a plurality of transistors (Q1, Q2; Q3, Q4; Q5, Q6; Q7, Q8) which are not simultaneously selected are converted into voltages using common resistors (R1) to (R4). These voltages then are fed to I/O ports (P1) to (P4). Accordingly, even upon a rise of a contact input from a ground potential due to the ON resistance of switches (SW1) to (SW8), the states of the contacts can be judged precisely.
    Type: Application
    Filed: September 23, 2005
    Publication date: April 20, 2006
    Applicant: Sumitomo Wiring Systems, Ltd.
    Inventor: Tsuyoshi Hosono
  • Publication number: 20040011155
    Abstract: The present apparatus comprises an accelerator pedal 10, a pedal arm 20, a pedal shaft 30 which supports the pedal arm 20 free to swing, a return spring 40, a friction generating mechanism 50 which generates friction force in accordance with the movement of the pedal arm 20, an accelerator position sensor 60 and a control segment 70 which controls an opening of a throttle valve 110 in accordance with an output signal of the sensor 60, wherein a play range in which friction force equal to or larger than a specific level is not generated is set to the friction generating mechanism in the range where the pedal arm moves from the resting position by a specific amount, and in the play range, an output signal of the accelerator position sensor 60 is kept constant resulting in that the throttle valve is kept at a specific opening. In this manner, desirable operating feeling without unsuitable feeling with the accelerator pedal operation is obtained while the accelerator apparatus is being compact and so on.
    Type: Application
    Filed: April 2, 2003
    Publication date: January 22, 2004
    Inventors: Masato Kumamoto, Takumi Oikawa, Tsuyoshi Hosono
  • Patent number: 5217897
    Abstract: This invention relates to a process for producing stigma-like tissues of saffron in a large scale by cutting the tissues of stigma (c), style (d, e, f), ovary (h, i, k), ovule (j), and petal (r) of saffron flower, and subculturing them on a liquid or solid LS medium or B5 medium containing a cytokinin and an auxin as main hormones.
    Type: Grant
    Filed: February 9, 1990
    Date of Patent: June 8, 1993
    Assignee: Ohta's Isan Co., Ltd.
    Inventors: Hiroshi Kohda, Kazuo Yamasaki, Atsuko Koyama, Hideki Miyagawa, Naomi Fujioka, Yuki Omori, Yoshiaki Ohta, Hiroshi Itoh, Tsuyoshi Hosono