Abstract: The present invention aims to eliminate reading operation of control information from a memory by a communication control apparatus, to reduce the time required for sending process and to improve the system performance. The communication control apparatus connected to a processor executing an operating system (OS) and applications, for sending data to an outside device, has a communication control information table for specifying send control information received from the OS. On receiving a send activation instruction from the processor, the communication control apparatus specifies an address of the memory based on the instruction and contents of the send control information table, reads the data from the memory, and starts to send the data to a receiver.

Abstract: The present invention aims to provide a control apparatus for controlling a hardware to be controlled such as a hardware for data transfer, especially a control apparatus for controlling at a high speed and steadily. A task identifying circuit connected to an address/control bus outputs a signal of a task identifier specified by at least a part of a received address. A write controlling unit outputs a write control signal based on the received address and a write request, and a task register stores the task identifier at a timing of the write control signal. A command register inputs a command from a data bus, and a data transferring circuit transfers the data based on the data stored in the register.

Abstract: A straight line generator for line drawing in a discrete coordinate system utilizing the Bresenham algorithm. A first counter holds an X coordinate value and is capable of incrementing and decrementing the X coordinate value and a second counter holds a Y coordinate value and is capable of incrementing and decrementing the Y coordinate value. A region code which depends on the slope of the line within the range of 360 degrees is stored. An error term obtained from the Bresenham algirithm is also stored. Responsive to the region code and the error term, increments of the first and second counters are controlled. Positive and negative added parameters which vary the error are stored in registers. Either of the date in the register is selected in accordance with the sign of the error term so as to be added to the error term.