Abstract: An embodiment is a computer system for processing input data, the system including a plurality of calculators, and a host connected to the plurality of calculators configured to control the plurality of calculators, wherein the processed data is configured to be transferred between the plurality of calculators, the calculator includes a trace buffer configured to record trace data upon detection of a predetermined event from the input data, and the trace data has a timestamp value that is the detection time of the event.

Abstract: AI inference system includes an encoder circuit that encodes an image captured by a camera, a decoder circuit that decodes the image, a first inference processing unit that executes first inference processing on the decoded image for each frame, a second inference processing unit that executes second inference processing with higher accuracy than the first inference only for frames of an image whose confidence value of the first inference exceeds a predetermined threshold, and a frame rate control unit that reduces frame rates of the encoder circuit and the decoder circuit from an initial value to a low speed value when the confidence value is equal to or less than the predetermined threshold.

Abstract: A relay system relays data transmitted to any one of a plurality of transmission destinations, and includes a reception unit that receives the data, a conversion unit that converts the data received by the reception unit into an optical signal having a wavelength varying according to a transmission destination to which the data is to be transmitted among the plurality of transmission destinations, and an output unit that outputs the optical signal converted by the conversion unit to an optical transmission line.

Abstract: A computing machine is a computing machine capable of adding or deleting a computational resource R for processing input data input from outside, and includes: a state information acquisition unit that acquires state information indicating a state of the computing machine; and a performance estimation unit that estimates, on the basis of the state indicated by the state information, a change in processing performance of the computing machine when at least one of dynamic addition or deletion of a computational resource or an increase in data amount of the input data or output data occurs.

Abstract: A computing system includes top-of-rack switches, a spine switch, and PIN blades arranged between the top-of-rack switches and resource blades. Each of the PIN blades includes a plurality of processing blocks, and each of the processing blocks includes a functional unit that performs predetermined processing on data included in the received packet.

Abstract: An embodiment is an electronic computer including a plurality of arithmetic circuits which sequentially execute a plurality of processings on a processing data, and a controller which executes a program and performs a control of causing the plurality of arithmetic circuits to sequentially execute the plurality of processings. An arithmetic circuit ID is imparted to each of the plurality of arithmetic circuits, the plurality of arithmetic circuits include a first arithmetic circuit that executes a first processing among the plurality of processings, and a second arithmetic circuit that executes a second processing that executes processing on a processing result of the first processing among the plurality of processings, and the first arithmetic circuit transmits the processing result of the first processing to the arithmetic circuit ID of the second arithmetic circuit as a destination.

Abstract: An embodiment is a computer system which processes input data which includes a plurality of arithmetic parts; and a host part connected to the plurality of arithmetic parts and configured to control the plurality of arithmetic parts, in which the processed data is transferred between the plurality of arithmetic parts, the arithmetic part includes trace parts which record trace data using detection of a predetermined event from the input data as a trigger, the trace data has a timestamp value which is a detection time of the event based on an operating frequency of the arithmetic part, and the timestamp values of the plurality of arithmetic parts are synchronized.

Abstract: In accordance with an embodiment, a shopping support apparatus includes a reader, a memory, and a processor. The processor causes the reader to read a data code, obtains store-specific setting information, and causes the memory to store control mode information included in the obtained setting information. The processor determines, on the basis of the control mode information of the setting information stored in the memory, whether to set a first mode for shopping support at the store as the control mode of the processor or set a second mode for a task restricted to an operation of an authorized person as the control mode of the processor.

Abstract: An imaging device according to an embodiment of the present disclosure includes: a first substrate including a sensor pixel that performs photoelectric conversion; a second substrate including a pixel circuit that outputs a pixel signal on a basis of electric charges outputted from the sensor pixel; and a third substrate including a processing circuit that performs signal processing on the pixel signal. The first substrate, the second substrate, and the third substrate are stacked in this order, and a low-permittivity region is provided in at least any region around a circuit that reads electric charges from the sensor pixel and outputs the pixel signal.

Abstract: A distributed deep learning system that can achieve speeding-up by processing learning in parallel at a large number of learning nodes connected with a communication network and perform faster cooperative processing among the learning nodes connected through the communication network is provided. The distributed deep learning system includes: a plurality of computing interconnect devices 1 connected with each other through a ring communication network 3 through which communication is possible in one direction; and a plurality of learning nodes 2 connected with the respective computing interconnect devices 1 in a one-to-one relation, and each computing interconnect device 1 executes communication packet transmission-reception processing between the learning nodes 2 and All-reduce processing simultaneously in parallel.

Abstract: A liquid ejection apparatus includes a liquid ejection head, a sensor, a carriage, and a controller. The controller is configured to perform: setting a first sheet at a first printing position; printing an image on the first sheet while conveying the first sheet from the first printing position; determining whether an interval is more than a predetermined period; in a case where the interval is determined to be more than the predetermined period: causing the carriage to move in a first direction to a first detection position at which a second sheet is detected; and in response to detecting the second sheet, causing the carriage to move in the first direction to a first carriage position.

Abstract: Compounds of Formula (I) or their pharmaceutically acceptable salts can inhibit the G12C, G12D and/or G12V mutants of Kirsten rat sarcoma (KRAS) protein and are expected to have utility as therapeutic agents, for example, for treating cancer. The disclosure also provides pharmaceutical compositions which comprise compounds of Formula (I) or pharmaceutically acceptable salts thereof. The disclosure also relates to methods for use of the compounds or their pharmaceutically acceptable salts in the therapy and prophylaxis of cancer and for preparing pharmaceuticals for this purpose.

Abstract: A laminate that permits passage of electromagnetic waves includes a base layer made of synthetic resin and a colored layer that contains a filler made of metal. The colored layer permits the passage of electromagnetic waves and has a relative permittivity of 4.0 or greater.

Abstract: An object of the present invention is to provide a compound having an anti-inflammatory activity or a pharmacologically acceptable salt thereof. The solution of the present invention is a compound of general formula (1) or a pharmacologically acceptable salt thereof. wherein the symbols in the formula are defined below: R1: e.g., a C1-C6 alkyl group; R2: a C1-C6 alkyl group; A: e.g., an oxygen atom; and R3: e.g., a C1-C6 alkyl group.

Abstract: An oxide film (4) is provided on an upper surface of the semiconductor substrate (1). A guard ring (3) is provided on the upper surface of the semiconductor substrate (1). An organic insulating film (6) directly contacts the oxide film (4) in a termination region (7) between the guard ring (3) and an outer edge portion of the semiconductor substrate (1). A groove (8) is provided on the upper surface of the semiconductor substrate (1) in the termination region (7). The groove (8) is embedded with the organic insulating film (6).

Abstract: A integrated light source module includes a planar optical waveguides layer having N light incident ports aligned with respect to each other, M light exit ports aligned with respect to each other, and optical waveguides connected to the N light incident ports and the M light exit ports, and N optical semiconductor devices facing each of the N light incident ports arranged so that light emitted from each of the N optical semiconductor devices can be incident on each of the N light incident ports, wherein light emitted from the M light exit ports can be applied to an object to be irradiated.

Abstract: An antenna device includes first and second coils. A portion of the first coil overlaps a coil opening of the second coil, and a portion of the second coil overlaps a coil opening of the first coil. The first coil includes a first coil conductor on a first surface of a base material and a first coil conductor on a second surface. The first coil includes a single-layer portion in which the first coil conductor is only on the first surface of the base material, and the second coil conductor intersects the first coil conductor at a portion facing the single-layer portion on the second surface of the base material.

Abstract: A computing system includes a first computer for writing an arithmetic circuit in a reconfigurable first region included in a first accelerator and a second computer for writing the arithmetic circuit in a reconfigurable second region included in a second accelerator different from the first accelerator and having the same circuit arrangement as the first region. When the first computer writes a new arithmetic circuit in the first region, the second computer writes the new arithmetic circuit in a partial region of the second region at the same position as the unwritten partial region of the first region. The first computer does not write the new arithmetic circuit in the first region when the new arithmetic circuit is not normally written, and writes the new arithmetic circuit in the unwritten partial region of the first region when the new arithmetic circuit is normally written.

Abstract: Each NIC performs an aggregation calculation of data output from each processor in a normal order including a head NIC located at a head position of a first pipeline connection, an intermediate NIC located at an intermediate position, and a tail NIC located at a tail position, and when the aggregation calculation in the tail NIC is completed, each NIC starts distribution of an obtained aggregation result, distributes the aggregation result in a reverse order including the tail NIC, the intermediate NIC, and the head NIC, and outputs the aggregation result to the processor of the communication interface.

Abstract: An imaging device according to an embodiment of the present disclosure includes: a first substrate including a sensor pixel that performs photoelectric conversion; a second substrate including a pixel circuit that outputs a pixel signal on a basis of electric charges outputted from the sensor pixel; and a third substrate including a processing circuit that performs signal processing on the pixel signal. The first substrate, the second substrate, and the third substrate are stacked in this order, and a low-permittivity region is provided in at least any region around a circuit that reads electric charges from the sensor pixel and outputs the pixel signal.