Patents by Inventor Tsuyoshi Jouno

Tsuyoshi Jouno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit device with test mode for testing CPU using external Signal
    Patent number: 5581698
    Abstract: An output gate means is provided which is capable of outputting individual signals selectively to an internal bus; the individual signals are interchanged among a plurality of functional modules connected to the internal bus which is interfaced with an external circuit. An input gate means is provided which is capable of supplying selectively a signal, input to the internal bus, to a specified functional module in place of an individual signal.
    Type: Grant
    Filed: April 15, 1993
    Date of Patent: December 3, 1996
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd.
    Inventors: Yoshiyuki Miwa, Tsuyoshi Jouno, Haruo Keida, Kunihiko Nakada, Hajime Yasuda