Patents by Inventor Tsuyoshi Kanao

Tsuyoshi Kanao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230411200
    Abstract: A method of manufacturing a semiconductor device includes: a grind step of forming a small thickness portion and a large thickness portion surrounding the small thickness portion in plan view by grinding a back surface of a semiconductor wafer; a preparation step of preparing a wafer holding member including a wafer placement surface and a back surface opposite to the wafer placement surface and having a larger thickness than a difference between a thickness of the large thickness portion and a thickness of the small thickness portion; and a placement step of placing the semiconductor wafer on the wafer holding member so that the small thickness portion of the semiconductor wafer and the wafer placement surface of the wafer holding member are in contact with each other on the back surface side of the semiconductor wafer.
    Type: Application
    Filed: March 28, 2023
    Publication date: December 21, 2023
    Inventors: Tsuyoshi KANAO, Koji OGATA
  • Patent number: 6747466
    Abstract: A substrate testing apparatus includes a first rail group made of a plurality of rails disposed in parallel with each other, a second rail group made of a plurality of rails disposed in parallel with each other in a direction that crosses the first rail group, a plurality of probe units disposed to cover respective intersections of the rails included in the first rail group and the rails included in the second rail group and being movable along the rails included in the first rail group and the second rail group, and corresponding interval maintaining means for keeping each rail included in the first rail group at an interval corresponding to an arrangement of locations to be measured on a substrate subjected to measurement, wherein the plurality of probe units each include a probing needle to be brought into contact with a surface of the substrate.
    Type: Grant
    Filed: November 16, 2001
    Date of Patent: June 8, 2004
    Assignees: Renesas Technology Corp., Ryoden Semiconductor System Engineering Corporation
    Inventors: Hiromitsu Sugimoto, Tsuyoshi Kanao
  • Publication number: 20020190736
    Abstract: A substrate testing apparatus includes a first rail group made of a plurality of rails disposed in parallel with each other, a second rail group made of a plurality of rails disposed in parallel with each other in a direction that crosses the first rail group, a plurality of probe units disposed to cover respective intersections of the rails included in the first rail group and the rails included in the second rail group and being movable along the rails included in the first rail group and the second rail group, and corresponding interval maintaining means for keeping each rail included in the first rail group at an interval corresponding to an arrangement of locations to be measured on a substrate subjected to measurement, wherein the plurality of probe units each include a probing needle to be brought into contact with a surface of the substrate.
    Type: Application
    Filed: November 16, 2001
    Publication date: December 19, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Hiromitsu Sugimoto, Tsuyoshi Kanao
  • Patent number: 6194907
    Abstract: A prober can make an appropriate evaluation in a microcurrent region. A wafer (9) is disposed on a chuck (8) in a casing (1). In the upper surface of the chuck (8), an electrode (8a) is formed which is connected to a power supply (11) via a wire (10). In the casing (1), a cylindrical electromagnetic shielding box (7) is disposed with the upper surface open. The upper surface of the casing (1) and the side surfaces and bottom surface of the electromagnetic shielding box (7) form a closed space (30) for surrounding the chuck (8) and the wafer (9). Also, a loader (6) for driving the chuck (8) and the electromagnetic shielding box (7) is disposed in the casing (1). On the upper surface of the casing (1), a tester head (3) is disposed with a probe card (4) disposed therein. Since part of the upper surface of the casing (1) is open, probe needles (5) of the probe card (4) protrude into the casing (1) through the opening.
    Type: Grant
    Filed: June 7, 1999
    Date of Patent: February 27, 2001
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Tsuyoshi Kanao, Koji Eguchi, Toru Yamaguchi