Patents by Inventor Tsuyoshi Kawagoe
Tsuyoshi Kawagoe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230282618Abstract: A semiconductor device is provided with: a reference unit in which at least two circuit modules are stacked with circuit layers adjoining each other; an additional unit in which at least two other circuit modules are stacked with circuit layers adjoining each other, the additional unit being stacked on the reference unit; and a via disposed through the reference unit and the additional unit and extending in a stacking direction. The via includes a reference via disposed in the reference unit, and an additional via disposed in the additional unit. The additional via at the position of contact with the reference via has a diameter smaller than a diameter of the reference via.Type: ApplicationFiled: July 16, 2020Publication date: September 7, 2023Inventors: Ichiro HOMMA, Tsuyoshi KAWAGOE
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Publication number: 20130248809Abstract: As for a variable resistive element including first and second electrodes, and a variable resistor containing a metal oxide between the first and second electrodes, in a case where a current path having a locally high current density of a current flowing between the both electrodes is formed in the metal oxide, and resistivity of at least one specific electrode having higher resistivity of the both electrodes is 100 ??cm or more, a dimension of a contact region of the specific electrode with the variable resistor in a short side or short axis direction is set to be more than 1.4 times as long as a film thickness of the specific electrode, which reduces variation in parasitic resistance generated in an electrode part due to process variation of the electrode, and prevents variation in resistance change characteristics of the variable resistive element generated due to the variation in parasitic resistance.Type: ApplicationFiled: March 22, 2013Publication date: September 26, 2013Applicants: ELPIDA MEMORY, INC., SHARP KABUSHIKI KAISHAInventors: Yukio TAMAI, Takashi NAKANO, Nobuyoshi AWAYA, Kazuo AIZAWA, Isamu ASANO, Naoya HIGANO, Tsuyoshi KAWAGOE
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Patent number: 8513638Abstract: A semiconductor device may include, but is not limited to: a first insulating film; a second insulating film over the first insulating film; a first memory structure between the first and second insulating films; and a third insulating film between the first and second insulating films. The first memory structure may include, but is not limited to: a heater electrode; and a phase-change memory element between the heater electrode and the second insulating film. The phase-change memory element contacts the heater electrode. The third insulating film covers at least a side surface of the phase-change memory element. Empty space is positioned adjacent to at least one of the heater electrode and the third insulating film.Type: GrantFiled: September 2, 2011Date of Patent: August 20, 2013Assignee: Elpida Memory, Inc.Inventors: Tomoyasu Kakegawa, Isamu Asano, Tsuyoshi Kawagoe, Hiromi Sasaoka, Naoya Higano, Yuta Watanabe
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Publication number: 20120056148Abstract: A semiconductor device may include, but is not limited to: a first insulating film; a second insulating film over the first insulating film; a first memory structure between the first and second insulating films; and a third insulating film between the first and second insulating films. The first memory structure may include, but is not limited to: a heater electrode; and a phase-change memory element between the heater electrode and the second insulating film. The phase-change memory element contacts the heater electrode. The third insulating film covers at least a side surface of the phase-change memory element. Empty space is positioned adjacent to at least one of the heater electrode and the third insulating film.Type: ApplicationFiled: September 2, 2011Publication date: March 8, 2012Applicant: ELPIDA MEMORY, INC.Inventors: Tomoyasu Kakegawa, Isamu Asano, Tsuyoshi Kawagoe, Hiromi Sasaoka, Naoya Higano, Yuta Watanabe
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Publication number: 20100302842Abstract: A semiconductor memory device includes: first and second impurity diffusion layers that form a part of a semiconductor substrate, each of the impurity diffusion layers function as one and the other of an anode and a cathode, respectively of a pn-junction diode; a recording layer connected to the second impurity diffusion layer; and a cylindrical sidewall insulation film provided on the first impurity diffusion layer. At least a part of the second diffusion layer and at least a part of the recording layer are formed in a region surrounded by a sidewall insulation film. According to the present invention, because a pillar-shaped pn-junction diode and the recording layer are formed in a self-aligned manner, the degree of integration of a semiconductor memory device can be increased. Further, because a silicon pillar is a part of the semiconductor substrate, a leakage current attributable to a crystal defect can be reduced.Type: ApplicationFiled: June 2, 2010Publication date: December 2, 2010Applicant: ELPIDA MEMORY, INC.Inventors: Tsuyoshi KAWAGOE, Isamu Asano
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Patent number: 7696504Abstract: A phase change memory device comprises an insulating layer and a phase change layer formed on the insulating layer. A phase change layer has a pad portion. The pad portion is formed with at least one slit.Type: GrantFiled: September 19, 2007Date of Patent: April 13, 2010Assignee: Elpida Memory, Inc.Inventor: Tsuyoshi Kawagoe
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Patent number: 7675770Abstract: A phase change memory device, comprising a phase change memory device; a semiconductor substrate; a MOS transistor disposed at each intersection of a plurality of word lines and a plurality of bit lines arranged in a matrix form; a plurality of phase change memory elements for storing data of a plurality of bits, each formed on an upper area opposite to a diffusion layer of the MOS transistor in a phase change layer made of phase change material; a lower electrode structure for electrically connecting each of the plurality of phase change memory elements to the diffusion layer of the MOS transistor.Type: GrantFiled: February 9, 2006Date of Patent: March 9, 2010Assignee: Elpida Memory, Inc.Inventors: Isamu Asano, Yukio Fuji, Kiyoshi Nakai, Tsuyoshi Kawagoe
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Patent number: 7554147Abstract: A memory device in which both DRAM and phase-change memory (PCRAM) are mounted is provided with a DRAM bit line, a PCRAM bit line or a PCRAM source line formed on an conductive layer shared with the DRAM bit line, and a sense amplifier connected between the DRAM bit line and the PCRAM bit line. The memory device further has a capacitive element disposed on the upper layer of the DRAM bit line, and a phase-change element disposed on the upper layer of the PCRAM bit line. The lower electrode of the capacitive element and the lower electrode of the phase-change memory element are formed on the shared conductive layer.Type: GrantFiled: March 14, 2006Date of Patent: June 30, 2009Assignee: Elpida Memory, Inc.Inventors: Isamu Asano, Tsuyoshi Kawagoe, Kiyoshi Nakai, Yukio Fuji, Kazuhiko Kajigaya
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Patent number: 7550756Abstract: In a semiconductor memory comprising a matrix of memory cells each composed of one transistor and one chalcogenide layer as a memory element, no chalcogenide layer is disposed at a joint between an upper electrode wire connected to the chalcogenide layer and another wiring layer.Type: GrantFiled: July 7, 2006Date of Patent: June 23, 2009Assignee: Elpida Memory, Inc.Inventors: Isamu Asano, Tsuyoshi Kawagoe
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Patent number: 7502252Abstract: For the purpose of providing a phase change memory device advantageous in layout and operation control by obtaining sufficient write current for high integrated phase change memory devices, the nonvolatile semiconductor memory device of the invention in which word lines and bit lines are arranged in a matrix-shape comprises a select transistor formed at each cross point of the word lines and the bit lines, and a plurality of memory elements commonly connected to the select transistor at one end and connected to a different element select line at an other end and which is capable of writing and reading data. Write and read operations for the selected memory element are controlled by supplying a predetermined current through the select transistor and through the element select line connected to the selected memory element, and the element select lines are arranged in parallel with the bit lines.Type: GrantFiled: October 25, 2005Date of Patent: March 10, 2009Assignee: Elpida Memory Inc.Inventors: Yukio Fuji, Isamu Asano, Tsuyoshi Kawagoe, Kiyoshi Nakai
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Patent number: 7449711Abstract: A phase-change memory device includes a plurality of bit lines extending in a row direction, a plurality of selection lines extending in a column direction, and an array of memory cells each disposed at one of intersections between the bit lines and selection lines. Each memory cell includes a chalcogenide element and a diode connected in series, and an n-type contact layer underlying the n-type layer of the diode. Adjacent two of memory cells share a common bit-line contact plug connecting the n-type contact layers and the bit line.Type: GrantFiled: January 11, 2006Date of Patent: November 11, 2008Assignee: Elpida Memory, Inc.Inventors: Isamu Asano, Tsuyoshi Kawagoe, Yukio Fuji, Kiyoshi Nakai, Kazuhiko Kajigaya
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Publication number: 20080067488Abstract: A phase change memory device comprises an Insulating layer and a phase change layer formed on the insulating layer. The phase change layer has a plurality of linear portions. The linear portions extend in a first direction are spaced from each other in a second direction perpendicular to the first direction. The neighboring ones of the linear portions have ends which open.Type: ApplicationFiled: September 19, 2007Publication date: March 20, 2008Applicant: ELPIDA MEMORY, INC.Inventor: Tsuyoshi KAWAGOE
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Publication number: 20080067487Abstract: A phase change memory device comprises an insulating layer and a phase change layer formed on the insulating layer. A phase change layer has a pad portion. The pad portion is formed with at least one slit.Type: ApplicationFiled: September 19, 2007Publication date: March 20, 2008Applicant: ELPIDA MEMORY, INC.Inventor: Tsuyoshi KAWAGOE
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Publication number: 20080043522Abstract: For the purpose of providing a phase change memory device advantageous in layout and operation control by obtaining sufficient write current for high integrated phase change memory devices, the nonvolatile semiconductor memory device of the invention in which word lines and bit lines are arranged in a matrix-shape comprises a select transistor formed at each cross point of the word lines and the bit lines, and a plurality of memory elements commonly connected to the select transistor at one end and connected to a different element select line at an other end and which is capable of writing and reading data. Write and read operations for the selected memory element are controlled by supplying a predetermined current through the select transistor and through the element select line connected to the selected memory element, and the element select lines are arranged in parallel with the bit lines.Type: ApplicationFiled: October 25, 2005Publication date: February 21, 2008Inventors: Yukio Fuji, Isamu Asano, Tsuyoshi Kawagoe, Kiyoshi Nakai
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Publication number: 20070148896Abstract: A semiconductor device includes memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of the MISFET for memory selection via a first metal layer and an upper electrode formed on the lower electrode via a capacitive insulating film. The lower electrode has a thickness of 30 nm or greater at the bottom portion thereof. Sputtering with a high ionization ratio and high directivity, such as PCM, is adapted to the formation of the lower electrode to make only the bottom portion of a capacitor thicker.Type: ApplicationFiled: November 27, 2006Publication date: June 28, 2007Inventors: Yoshitaka Nakamura, Hidekazu Goto, Isamu Asano, Mitsuhiro Horikawa, Keiji Kuroki, Hiroshi Sakuma, Kenichi Koyanagi, Tsuyoshi Kawagoe
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Publication number: 20070141786Abstract: A method of manufacturing a non-volatile memory element in the present invention comprises a first step for forming an adhesion layer on an interlayer insulating film so that an electrical connection is established with a lower electrode, a second step for forming a recording layer containing a phase change material on the adhesion layer, a third step for forming an upper electrode that is electrically connected to the recording layer, and a fourth step for diffusing in the recording layer some of the adhesion layer positioned between at least the lower electrode and the recording layer.Type: ApplicationFiled: December 12, 2006Publication date: June 21, 2007Inventors: Tsuyoshi Kawagoe, Isamu Asano
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Patent number: 7224016Abstract: A semiconductor device includes memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of the MISFET for memory selection via a first metal layer and an upper electrode formed on the lower electrode via a capacitive insulating film. The lower electrode has a thickness of 30 nm or greater at the bottom portion thereof. Sputtering with a high ionization ratio and high directivity, such as PCM, is adapted to the formation of the lower electrode to make only the bottom portion of a capacitor thicker.Type: GrantFiled: February 13, 2004Date of Patent: May 29, 2007Assignees: Elpida Memory, Inc., Hitachi ULSI Systems, Co., Ltd., Hitachi Ltd.Inventors: Yoshitaka Nakamura, Hidekazu Goto, Isamu Asano, Mitsuhiro Horikawa, Keiji Kuroki, Hiroshi Sakuma, Kenichi Koyanagi, Tsuyoshi Kawagoe
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Publication number: 20070090336Abstract: In a semiconductor memory comprising a matrix of memory cells each composed of one transistor and one chalcogenide layer as a memory element, no chalcogenide layer is disposed at a joint between an upper electrode wire connected to the chalcogenide layer and another wiring layer.Type: ApplicationFiled: July 7, 2006Publication date: April 26, 2007Inventors: Isamu Asano, Tsuyoshi Kawagoe
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Patent number: 7183170Abstract: After an upper electrode protective film is formed such that it is in a firm contact with ruthenium film of the upper electrode without damaging the ruthenium film, the upper electrode is etched, thereby, a MIM capacitor is obtained in which leak current is not increased due to oxidation of the ruthenium film of the upper electrode.Type: GrantFiled: November 30, 2004Date of Patent: February 27, 2007Assignee: Elpida Memory, Inc.Inventors: Yoshitaka Nakamura, Tsuyoshi Kawagoe, Hiroshi Sakuma, Isamu Asano, Keiji Kuroki, Hidekazu Goto, Shinpei Iijima
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Patent number: 7141471Abstract: A sidewall insulating film (11) made of a silicon oxide film is formed on the sidewall of a gate electrode (7) (word line) with an aim to reduce the capacitance to the word line serving as the major component of the bit line capacitance. Also, when openings for connecting the bit lines are formed above the spaces of the gate electrodes (7) (word lines) by the dry etching of a silicon oxide film (31) above contact holes (12), a silicon nitride film (19) to be an etching stopper is provided below the silicon oxide film (31) so as to reduce the amount of the bottom surface of the opening receded below the upper surface of a cap insulating film (9).Type: GrantFiled: February 7, 2002Date of Patent: November 28, 2006Assignee: Elpida Memory, Inc.Inventors: Satoru Yamada, Hiroyuki Enomoto, Nobuya Saito, Tsuyoshi Kawagoe, Hisaomi Yamashita