Abstract: To resolve volume shortage of middle and high band of speaker reproduction sound. A DSP 4 performs LPF processing to extract low frequency component of an audio signal to which the first volume processing is performed, DRC processing to compress the audio signal to which the LPF processing is performed in case that the audio signal to which the LPF processing is performed is not less than a predetermined signal level, HPF processing to extract high frequency component of the audio signal to which the first volume processing is performed, second volume processing to attenuate the audio signal to which the HPF processing is performed based on the volume value that is received, and synthesis processing to synthesize the audio signal to which the DRC processing is performed and the audio signal to which the second volume processing is performed.

Abstract: A first circuit unit of an audio amplifier includes a first emitter follower connected to an pre stage input terminal, a second emitter follower connected to an pre stage input terminal, a main transistor connected to an output path of the first emitter follower and an output path of the second emitter follower, a first resistor and a second resistor, which are series-connected between the output path of the first emitter follower and a DC voltage source, and a zener diode connected to a series-connection point between the first resistor and the second resistor. A second circuit unit has a circuit configuration that is complementary to the first circuit unit. A path leading to a collector of each transistor configuring the first and second emitter followers in one of the circuit units is connected to the series-connection point in the other circuit unit.

Abstract: To resolve volume shortage of middle and high band of speaker reproduction sound. A DSP 4 performs LPF processing to extract low frequency component of an audio signal to which the first volume processing is performed, DRC processing to compress the audio signal to which the LPF processing is performed in case that the audio signal to which the LPF processing is performed is not less than a predetermined signal level, HPF processing to extract high frequency component of the audio signal to which the first volume processing is performed, second volume processing to attenuate the audio signal to which the HPF processing is performed based on the volume value that is received, and synthesis processing to synthesize the audio signal to which the DRC processing is performed and the audio signal to which the second volume processing is performed.

Abstract: Provided is a modulation circuit that can correct an output state in real time and reliably modulate an input signal to output the modulated signal. The signal modulation circuit includes a subtractor, an integrator, a chopper circuit, a frequency divider, and a D-type flip-flop. A delay circuit of a sigma delta modulation circuit is not provided to a feedback circuit, and a signal is delayed and quantized in the D-type flip-flop. The chopper circuit inserts a zero level at timing synchronized with a clock signal, so that pulse density modulation is performed.

Abstract: To realize active control ground that sets inverted output of an amplification circuit to ground with simple configuration. A DAP 1 comprises a positive side DAC 7 that D/A-converts digital audio data into analog audio data, a positive side amplification circuit 9 that amplifies the analog audio data that the DAC 7 D/A-converts, a negative side DAC 8 that D/A-converts the digital audio data into the analog audio data, and a negative side amplification circuit 10 that amplifies the analog audio data that the DAC 8 D/A-converts, and a CPU 2. The CPU 2 mutes the DAC 8 in case of an ACG mode that sets output of the amplification circuit 10 to ground.

Abstract: To reduce signal output and wiring to a D/A converter (DAC). A DAP 1 comprises a DAC 7 that D/A-converts LR 2 channels digital audio data into LR 2 channels analog audio data, an amplification circuit 9 that amplifies the LR 2 channels analog audio data that the DAC 7 D/A-converts, a DAC 8 that D/A-converts the LR 2 channels digital audio data into the LR 2 channels analog audio data, and an amplification circuit 10 that amplifies inverted LR 2 channels analog audio data that the LR 2 channels analog audio data that the DAC 8 D/A-converts is inverted.

Abstract: Provided is a circuit which can correct an output state in real time and reduce influences of distortion/noise components generated by a delay device. A signal modulation circuit includes a subtractor, an integrator, a phase inverting circuit, a DFF for while inserting a zero level at timing synchronous with the clock signal, delaying and quantizing the signal, a ternary signal generating circuit for generating a ternary signal for selectively driving a load connected to a single power supply into ternary conductive states including a positive current on-state, a negative current on-state, and an off-state, a driver circuit for generating a driving signal for driving a load, and a feedback circuit for feeding back the driving signal from the driver circuit to the input signal.

Abstract: To reduce signal output and wiring to a D/A converter (DAC). A DAP 1 comprises a DAC 7 that D/A-converts LR 2 channels digital audio data into LR 2 channels analog audio data, an amplification circuit 9 that amplifies the LR 2 channels analog audio data that the DAC 7 D/A-converts, a DAC 8 that D/A-converts the LR 2 channels digital audio data into the LR 2 channels analog audio data, and an amplification circuit 10 that amplifies inverted LR 2 channels analog audio data that the LR 2 channels analog audio data that the DAC 8 D/A-converts is inverted.

Abstract: To realize active control ground that sets inverted output of an amplification circuit to ground with simple configuration. A DAP 1 comprises a positive side DAC 7 that D/A-converts digital audio data into analog audio data, a positive side amplification circuit 9 that amplifies the analog audio data that the DAC 7 D/A-converts, a negative side DAC 8 that D/A-converts the digital audio data into the analog audio data, and a negative side amplification circuit 10 that amplifies the analog audio data that the DAC 8 D/A-converts, and a CPU 2. The CPU 2 mutes the DAC 8 in case of an ACG mode that sets output of the amplification circuit 10 to ground.

Abstract: A signal modulation circuit includes a feedback circuit configured to generate the feedback signal for feeding back a drive signal from a driver circuit to an input signal. The feedback circuit includes at least first and second resistors connected together in series, the second resistor having a higher resistance value than that of the first resistor. One end of the first resistor is connected to a subtracter, and one end of the second resistor is connected to the driver circuit. A first line distance as the line length between one end of the first resistor and the subtracter and a second line distance as the line length between one end of the second resistor and the driver circuit are set shorter than a third line distance as the line length between the other end of the first resistor and the other end of the second resistor.

Abstract: Provided is a modulation circuit that can correct an output state in real time and reliably modulate an input signal to output the modulated signal. The signal modulation circuit includes a subtractor, an integrator, a chopper circuit, a frequency divider, and a D-type flip-flop. A delay circuit of a sigma delta modulation circuit is not provided to a feedback circuit, and a signal is delayed and quantized in the D-type flip-flop. The chopper circuit inserts a zero level at timing synchronized with a clock signal, so that pulse density modulation is performed.

Abstract: Provided is a head-up display device that can be aesthetically pleasing, thereby improving marketability. A HUD device is provided with: a display device that outputs display light that represents a display image; a combiner that has a concave surface to which the display light output by the display device falls incident, said combiner concentrating the incident display light so as to allow an observer to see the display image from the concave surface side superimposed on a background in front; and an optical sensor that is positioned so as to face the concave surface and detects the brightness of external light that passes through the combiner and falls incident thereon.

Abstract: Provided is a modulation circuit that can correct an output state in real time and reliably modulate an input signal to output the modulated signal. The signal modulation circuit includes a subtracter, an integrator, a chopper circuit, a frequency divider, and a D-type flip-flop. A delay circuit of a sigma delta modulation circuit is not provided to a feedback circuit, and a signal is delayed and quantized in the D-type flip-flop. The chopper circuit inserts a zero level at timing synchronized with a clock signal, so that pulse density modulation is performed.

Abstract: A circuit having versatility synthesizes one-bit digital signals to generate a ternary signal. The pulse synthesizing circuit synthesizes one-bit digital signals from two DFFs to generate a ternary signal. The pulse synthesizing circuit has a first NOR gate, a second NOR gate, a third NOR gate, and three switches. The first switch is connected to a first electric potential, the second switch is connected to a second electric potential, and the third switch is connected to a third electric potential. The first to third switches are turned on/off according to logical values of the signals from the two DFFs, and any of the first electric potential, the second electric potential, and the third electric potential is set as an output potential so that a ternary signal is generated.

Abstract: Provided is a head-up display device that can detect background brightness with a simple constitution. A HUD device (1) is provided with: a display device (20) that outputs display light (L) that shows a display image; a combiner (50) that has a concave surface (50a) to which the display light (L) output by the display device (20) is incident, said combiner (50) concentrating the incident display light (L) so as to allow an observer (2) to see the display image from the concave surface (50a) side superimposed on a background from the front; and an optical sensor (31) that is positioned below the combiner (50) and detects the brightness of the light reaching that optical sensor (31). The combiner (50) has a light guide body (60) which is at the lower edge part thereof and is integrated with the combiner (50).

Abstract: An amplifying device is provided that reduces power consumption and quickly starts amplification of an audio signal of a channel to be used. A control section 17 inputs a control signal for instructing operation or standby into post-amplifying sections 11b and 12b, and inputs a control signal for instructing standby to post-amplifying sections 13b and 14b. In the post-amplifying section 11b, when the control signal for instructing standby or operation is input from the control section 17, a modulation circuit 52 modulates the analog audio signal into a switching signal. An output stage circuit 54 amplifies the output signal. When the control signal for instructing the operation is input from the control section 17, a driving circuit 53 drives the output stage circuit 54 in response to the switching signal, and stops the driving of the output stage circuit 54 when the control signal for instructing standby is input.

Abstract: A circuit having versatility synthesizes one-bit digital signals to generate a ternary signal. The pulse synthesizing circuit synthesizes one-bit digital signals from two DFFs to generate a ternary signal. The pulse synthesizing circuit has a first NOR gate, a second NOR gate, a third NOR gate, and three switches. The first switch is connected to a first electric potential, the second switch is connected to a second electric potential, and the third switch is connected to a third electric potential. The first to third switches are turned on/off according to logical values of the signals from the two DFFs, and any of the first electric potential, the second electric potential, and the third electric potential is set as an output potential so that a ternary signal is generated.

Abstract: Provided is a circuit which can correct an output state in real time and reduce influences of distortion/noise components generated by a delay device. A signal modulation circuit includes a subtractor, an integrator, a phase inverting circuit, a DFF for while inserting a zero level at timing synchronous with the clock signal, delaying and quantizing the signal, a ternary signal generating circuit for generating a ternary signal for selectively driving a load connected to a single power supply into ternary conductive states including a positive current on-state, a negative current on-state, and an off-state, a driver circuit for generating a driving signal for driving a load, and a feedback circuit for feeding back the driving signal from the driver circuit to the input signal.

Abstract: Provided is a head-up display device that can detect background brightness with a simple constitution. A HUD device (1) is provided with: a display device (20) that outputs display light (L) that shows a display image; a combiner (50) that has a concave surface (50a) to which the display light (L) output by the display device (20) is incident, said combiner (50) concentrating the incident display light (L) so as to allow an observer (2) to see the display image from the concave surface (50a) side superimposed on a background from the front; and an optical sensor (31) that is positioned below the combiner (50) and detects the brightness of the light reaching that optical sensor (31). The combiner (50) has a light guide body (60) which is at the lower edge part thereof and is integrated with the combiner (50).

Abstract: A circuit having versatility synthesizes one-bit digital signals to generate a ternary signal. The pulse synthesizing circuit synthesizes one-bit digital signals from two DFFs to generate a ternary signal. The pulse synthesizing circuit has a first NOR gate, a second NOR gate, a third NOR gate, and three switches. The first switch is connected to a first electric potential, the second switch is connected to a second electric potential, and the third switch is connected to a third electric potential. The first to third switches are turned on/off according to logical values of the signals from the two DFFs, and any of the first electric potential, the second electric potential, and the third electric potential is set as an output potential so that a ternary signal is generated.