Patents by Inventor Tsuyoshi Kouchi

Tsuyoshi Kouchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10038086
    Abstract: A process of forming a High Electron Mobility Transistor (HEMT) made of nitride semiconductor materials is disclosed. The process sequentially grows a buffer layer, a n-type layer doped with n-type dopants, and a channel layer by a metal organic chemical vapor deposition (MOCVD) technique. A feature of the process is to supply only an n-type dopant gas before the growth of the n-type layer but after the growth of the buffer layer.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: July 31, 2018
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Ken Nakata, Tsuyoshi Kouchi, Isao Makabe, Keiichi Yui
  • Publication number: 20180053648
    Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes steps of forming an AlN layer on a SiC substrate under conditions of a growth temperature of 1100° C. or lower, growth pressure of 100 torr or less and a V/III ratio of source gasses of 500 or less, forming a channel layer made of a nitride semiconductor, forming an electron supply layer, and forming gate, source, and drain electrodes.
    Type: Application
    Filed: October 13, 2017
    Publication date: February 22, 2018
    Inventors: Ken Nakata, Keiichi Yui, Hiroyuki Ichikawa, Isao Makabe, Tsuyoshi Kouchi
  • Publication number: 20170271496
    Abstract: A High Electron Mobility Transistor (HEMT) made of nitride semiconductor materials and a process of forming the same are disclosed. The HEMT has a feature that an n-type layer doped with n-type dopants is provided between the buffer layer and the channel layer. The existence of the n-type layer with a substantial conductance beneath the channel layer suppresses the current collapsing and enhances the surface quality of the channel layer in spite of a thinned channel layer.
    Type: Application
    Filed: March 15, 2017
    Publication date: September 21, 2017
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Ken NAKATA, Tsuyoshi KOUCHI, lsao MAKABE, Keiichi YUi
  • Patent number: 9355843
    Abstract: A method of manufacturing a semiconductor device according to one aspect of the present invention includes a step of forming a first layer of InAlN, a step of forming a second layer of InAlGaN on the first layer under a growth temperature higher than that of the first layer, and a step of forming a third layer of GaN, AlGaN or InGaN under a growth temperature higher than that of the first layer.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: May 31, 2016
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiichi Yui, Ken Nakata, Tsuyoshi Kouchi, Isao Makabe
  • Publication number: 20160111274
    Abstract: A method for producing a nitride semiconductor device is disclosed. The method includes steps of: forming a channel layer, an InAlN doped layer sequentially on the substrate, raising a temperature of the substrate as supplying a gas source containing In, and/or another gas source containing Al, and growing GaN layer on the InAlN doped. Or, the method grows the channel layer, the InAlN layer, and another GaN layer sequentially on the substrate, raising the temperature of the substrate, and growing the GaN layer. These methods suppress the sublimation of InN from the InAlN layer.
    Type: Application
    Filed: December 30, 2015
    Publication date: April 21, 2016
    Inventors: Keiichi Yui, Ken Nakata, Isao Makabe, Tsuyoshi Kouchi
  • Publication number: 20150332915
    Abstract: A method of manufacturing a semiconductor device according to one aspect of the present invention includes a step of forming a first layer of InAlN, a step of forming a second layer of InAlGaN on the first layer under a growth temperature higher than that of the first layer, and a step of forming a third layer of GaN, AlGaN or InGaN under a growth temperature higher than that of the first layer.
    Type: Application
    Filed: July 27, 2015
    Publication date: November 19, 2015
    Inventors: Keiichi Yui, Ken Nakata, Tsuyoshi Kouchi, Isao Makabe
  • Patent number: 9159821
    Abstract: A GaN device suppressing the instantaneous current reduction after the shut-off of a high frequency signal is disclosed. The GaN device provides, on a SiC substrate, an AlN layer, a GaN layer, and an AlGaN layer, The SiC substrate has an energy difference greater than 0.67 eV but less than 1.43 eV; the AlN layer has a thickness less than 50 nm; and the GaN layer has a thickness less than 1.5 ?m.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: October 13, 2015
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Ken Nakata, Keiichi Yui, Hiroyuki Ichikawa, Tsuyoshi Kouchi
  • Publication number: 20150279658
    Abstract: A method to produce a nitride semiconductor device is disclosed, The method includes a step to grow sequentially, on a substrate, an AlN layer, a AlGaN layer with the Al composition not less than 2.5% but not greater than 9%, a GaN layer with a thickness not less than 250 nm but not greater than 1400 nm. A feature of the process is that, after the growth of the AlGaN layer but before the growth of the GaN layer, at least the source gases for the group III elements are interrupted to be supplied for a period of not less than 80 seconds but not longer than 220 seconds.
    Type: Application
    Filed: March 24, 2015
    Publication date: October 1, 2015
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Keiichi YUI, Ken Nakata, Isao Makabe, Tsuyoshi KOUCHI
  • Publication number: 20150279942
    Abstract: A process to obtain a nitride transistor containing a gallium nitride (GaN) is disclosed. The process first grows an AlN layer on a substrate, then crown the GaN layer cc the AlN layer. Between the growth of the AlN layer and the GaN layer, the process leaves the AlN layer grown art the substrate in a temperature higher than the growth temperature of the AlN layer for a preset period. This heat treatment of the AlN layer sublimates impurities accumulated on the surface of the AlN layer and enhances the crystal quality of the GaN layer grown thereon.
    Type: Application
    Filed: March 17, 2015
    Publication date: October 1, 2015
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Keiichi YUI, Ken Nakata, Isao Makabe, Tsuyoshi Kouchi
  • Patent number: 9123534
    Abstract: A method of manufacturing a semiconductor device according to one aspect of the present invention includes a step of forming a first layer of InAlN, a step of forming a second layer of InAlGaN on the first layer under a growth temperature higher than that of the first layer, and a step of forming a third layer of GaN, AlGaN or InGaN under a growth temperature higher than that of the first layer.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: September 1, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiichi Yui, Ken Nakata, Tsuyoshi Kouchi, Isao Makabe
  • Patent number: 9029873
    Abstract: The semiconductor device includes a SiC substrate; an aluminum nitride layer provided on the substrate and having an island-shaped pattern consisting of plural islands: a channel layer provided on the AlN layer and comprising a nitride semiconductor; an electron supplying layer provided on the channel layer and having a band gap larger than that of the channel layer; and a gate, source and drain electrodes on the electron supply layer. The AlN layer has an area-averaged circularity Y/X of greater than 0.2. Y is a sum of values obtained by multiplying circularities of the plural islands by areas of the plural islands respectively, X is a sum of the areas of the plural islands. The circularity are calculated by a formula of (4?×area)/(length of periphery)2 where the area and the length of periphery are an area and a length of periphery of each island.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: May 12, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Ken Nakata, Keiichi Yui, Tsuyoshi Kouchi, Isao Makabe, Hiroyuki Ichikawa
  • Publication number: 20140361308
    Abstract: A method of manufacturing a semiconductor device according to one aspect of the present invention includes a step of forming a first layer of InAlN, a step of forming a second layer of InAlGaN on the first layer under a growth temperature higher than that of the first layer, and a step of forming a third layer of GaN, AlGaN or InGaN under a growth temperature higher than that of the first layer.
    Type: Application
    Filed: June 5, 2014
    Publication date: December 11, 2014
    Inventors: Keiichi Yui, Ken Nakata, Tsuyoshi Kouchi, Isao Makabe
  • Publication number: 20140346530
    Abstract: A semiconductor device according to an embodiment of the present invention includes a SiC substrate, an AlN layer provided on the SiC substrate and having a maximum valley depth Rv of 5 nm or less in an upper surface, a channel layer provided on the AlN layer and composed of a nitride semiconductor, an electron supply layer provided on the channel layer and having a greater band gap than the channel layer, and a gate electrode, a source electrode and a drain electrode provided on the electron supply layer.
    Type: Application
    Filed: May 22, 2014
    Publication date: November 27, 2014
    Applicant: SUMITOMO ELECTRIC INDUSTIRES, LTD.
    Inventors: Ken NAKATA, Keiichi YUI, Hiroyuki ICHIKAWA, Isao MAKABE, Tsuyoshi KOUCHI
  • Publication number: 20140252377
    Abstract: The semiconductor device includes a SiC substrate; an aluminum nitride layer provided on the substrate and having an island-shaped pattern consisting of plural islands: a channel layer provided on the AlN layer and comprising a nitride semiconductor; an electron supplying layer provided on the channel layer and having a band gap larger than that of the channel layer; and a gate, source and drain electrodes on the electron supply layer. The AlN layer has an area-averaged circularity Y/X of greater than 0.2. Y is a sum of values obtained by multiplying circularities of the plural islands by areas of the plural islands respectively, X is a sum of the areas of the plural islands. The circularity are calculated by a formula of (4?×area)/(length of periphery)2 where the area and the length of periphery are an area and a length of periphery of each island.
    Type: Application
    Filed: March 5, 2014
    Publication date: September 11, 2014
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Ken NAKATA, Keiichi YUI, Tsuyoshi KOUCHI, Isao MAKABE, Hiroyuki ICHIKAWA
  • Publication number: 20140183563
    Abstract: A GaN device suppressing the instantaneous current reduction after the shut-off of a high frequency signal is disclosed. The GaN device provides, on a SiC substrate, an AlN layer, a GaN layer, and an AlGaN layer. The SiC substrate has an energy difference greater than 0.67 eV but less than 1.43 eV; the AlN layer has a thickness less than 50 nm; and the GaN layer has a thickness less than 1.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 3, 2014
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Ken NAKATA, Keiichi YUI, Hiroyuki ICHIKAWA, Tsuyoshi KOUCHI
  • Publication number: 20120315742
    Abstract: A method for producing a nitride semiconductor device is disclosed. The method includes steps of: forming a channel layer, an InAlN doped layer sequentially on the substrate, raising a temperature of the substrate as supplying a gas source containing In, and/or another gas source containing Al, and growing GaN layer on the InAlN doped. Or, the method grows the channel layer, the InAlN layer, and another GaN layer sequentially on the substrate, raising the temperature of the substrate, and growing the GaN layer. These methods suppress the sublimation of InN from the InAlN layer.
    Type: Application
    Filed: June 6, 2012
    Publication date: December 13, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Keiichi YUI, Ken NAKATA, Isao MAKABE, Tsuyoshi KOUCHI
  • Publication number: 20100248459
    Abstract: A method for fabricating a semiconductor device including: cleaning an apparatus used to grow a layer including Ga; performing a first step of forming a first layer on a substrate made of silicon by using the apparatus, the first layer including a nitride semiconductor that does not include Ga as a composition element and has a Ga impurity concentration of 2×1018 atoms/cm3 or less; and performing a second step of forming a second layer on the first layer by using the apparatus after the first step is repeatedly carried out multiple times, the second layer including a nitride semiconductor including Ga.
    Type: Application
    Filed: March 30, 2010
    Publication date: September 30, 2010
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Isao Makabe, Ken Nakata, Tsuyoshi Kouchi
  • Patent number: 6661557
    Abstract: There is provided an optical modulator in which positive holes produced in the valence band are not piled up, the electrostatic capacity can be decreased, the frequency response characteristic is improved, and which is capable of operating at a high speed. In an optical modulator comprising: an n-type clad layer; a stripe-like modulation layer elongated in the direction of light propagation and formed on the top surface of the n-type clad layer; a buffer layer formed on the top surface of the modulation layer; and a p-type clad layer formed on the top surface of the buffer layer, the buffer layer has its composition the band gap energy of which is higher by an energy due to a p-type acceptor level than that of the modulation layer, thereby to remove a difference in band gap energy between the modulation layer and the buffer layer.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: December 9, 2003
    Assignee: Japan Aviation Electronics Industry Limited
    Inventors: Tsuyoshi Kouchi, Takashi Mitsuma
  • Publication number: 20030123130
    Abstract: There is provided an optical modulator in which positive holes produced in the valence band are not piled up, the electrostatic capacity can be decreased, the frequency response characteristic is improved, and which is capable of operating at a high speed. In an optical modulator comprising: an n-type clad layer; a stripe-like modulation layer elongated in the direction of light propagation and formed on the top surface of the n-type clad layer; a buffer layer formed on the top surface of the modulation layer; and a p-type clad layer formed on the top surface of the buffer layer, the buffer layer has its composition the band gap energy of which is higher by an energy due to a p-type acceptor level than that of the modulation layer, thereby to remove a difference in band gap energy between the modulation layer and the buffer layer.
    Type: Application
    Filed: November 22, 2002
    Publication date: July 3, 2003
    Inventors: Tsuyoshi Kouchi, Takashi Mitsuma