Patents by Inventor Tsuyoshi Kuramoto

Tsuyoshi Kuramoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240125807
    Abstract: The purpose of the present invention is to provide a method for determining the fraction unbound (fu) of compounds including compounds having a high protein binding ratio with accuracy and in a short time.
    Type: Application
    Filed: December 17, 2021
    Publication date: April 18, 2024
    Inventors: Fumihiko IGARASHI, Tatsuhiko TACHIBANA, Tsuyoshi YAMAUCHI, Shino KURAMOTO, Fumiyo MATSUNO
  • Publication number: 20180238043
    Abstract: A greenhouse building has perimeter wall frames constituted by linear materials such as single pipes, and roof frames constituted by tension wires that are extended in a stretched state in the longitudinal and crosswise directions. The tension force of the tension wires is received by the installation surface through anchoring tension wires. Only compression force acts on support posts of the wall frames and substantially no bending force acts thereon. A large building can be easily constructed using linear materials such as single pipes with a small diameter. A large greenhouse with high light receiving efficiency can be easily constructed without using heavy building materials such as steel frame materials.
    Type: Application
    Filed: August 19, 2016
    Publication date: August 23, 2018
    Applicant: Komoro Nunobiki Strawberry Farm Co., Ltd.
    Inventor: Tsuyoshi Kuramoto
  • Patent number: 5065212
    Abstract: There is a semiconductor device in which an n-type layer formed on a p.sup.+ -type substrate is divided into first and second device forming regions by an isolation region and drive circuit devices and an output circuit device are respectively formed in these first and second device forming regions. The output circuit device is a conductivity modulated MOS transistor having the p.sup.+ -type substrate as a drain and the second device forming regoin as a high resistance region whose conductivity is modulated.
    Type: Grant
    Filed: November 13, 1989
    Date of Patent: November 12, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yu Ohata, Tsuyoshi Kuramoto
  • Patent number: 4948748
    Abstract: A substrate structure for a composite semiconductor device comprises first and second semiconductor substrates whose major surfaces are bonded to each other with an insulating layer interposed therebetween. In this substrate structure, an epitaxial layer is grown from part of the second semiconductor substrate, forming one element area, and another element area is formed in the first semiconductor substrate area and isolated from the epitaxial layer.
    Type: Grant
    Filed: August 21, 1989
    Date of Patent: August 14, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Kitahara, Yu Ohata, Tsuyoshi Kuramoto
  • Patent number: 4879584
    Abstract: A semiconductor device is provided which has a power insulated-gate MOS field effect transistor and a control semiconductor element formed in a common semiconductor substrate. A first area corresponding to a drain region of low resistance in the power MOS field effect transistor is different in resistivity than a second area corresponding to the control semiconductor element. The electrical characteristics of each element integrated in the devices is substantially equal to the same element in discrete form.
    Type: Grant
    Filed: February 10, 1988
    Date of Patent: November 7, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yosuke Takagi, Yu Ohata, Koichi Kitahara, Tsuyoshi Kuramoto
  • Patent number: 4837186
    Abstract: A silicon semiconductor substrate includes an insulating layer embedded therein. The silicon semiconductor substrate comprises a first silicon plate, an insulating layer embedded in the first silicon plate so that the surfaces of the silicon plate and the insulating layer are in a mirror surface, and a second silicon plate united with the first silicon plate and the insulating layer at the mirror surface of the first silicon plate and the insulating layer. The insulating layer is used for forming an isolated region in the second silicon plate.
    Type: Grant
    Filed: August 12, 1987
    Date of Patent: June 6, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yu Ohata, Tsuyoshi Kuramoto, Masaru Shimbo
  • Patent number: RE34025
    Abstract: A semiconductor device is provided which has a power insulated-gate MOS field effect transistor and a control semiconductor element formed in a common semiconductor substrate. A first area corresponding to a drain region of low resistance in the power MOS field effect transistor is different in resistivity than a second area corresponding to the control semiconductor element. The electrical characteristics of each element integrated in the devices is substantially equal to the same element in discrete form.
    Type: Grant
    Filed: November 28, 1990
    Date of Patent: August 11, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yosuke Takagi, Yu Ohata, Koichi Kitahara, Tsuyoshi Kuramoto