Patents by Inventor Tsuyoshi MORISAKI

Tsuyoshi MORISAKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9972491
    Abstract: According to one embodiment, there is provided a mask data generation method. The mask data generation method includes obtaining depth information about a pattern depth of a hole included in design information about a semiconductor device. The mask data generation method includes obtaining a first correction rule used to correct, in terms of the pattern depth, a process conversion difference between a resist pattern and a processed pattern. The mask data generation method includes determining temporary mask data including a lithography target pattern by applying a first process conversion difference correction processing to a dimension of hole pattern arranged in design layout data based on the depth information and the first correction rule.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: May 15, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tsuyoshi Morisaki, Satoshi Usui, Katsuhiro Ishiba
  • Patent number: 9858379
    Abstract: According to one embodiment, in a mask data generation system, a first acquisition part is configured to acquire pattern contour data included in each of a plurality of layout candidate data for a first layer. A second acquisition part is configured to acquire pattern contour data included in layout data for a second layer. A superimposing part is configured to superimpose the contour data acquired by the first acquisition part and the contour data acquired by the second acquisition part with each other, for each of the plurality of layout candidate data. An area calculation part is configured to calculate an overlap area between a first pattern in the contour data acquired by the first acquisition part and a second pattern in the contour data acquired by the second acquisition part, based on the superimposed data, for each of the plurality of layout candidate data.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: January 2, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tsuyoshi Morisaki, Satoshi Usui
  • Publication number: 20160239601
    Abstract: According to one embodiment, in a mask data generation system, a first acquisition part is configured to acquire pattern contour data included in each of a plurality of layout candidate data for a first layer. A second acquisition part is configured to acquire pattern contour data included in layout data for a second layer. A superimposing part is configured to superimpose the contour data acquired by the first acquisition part and the contour data acquired by the second acquisition part with each other, for each of the plurality of layout candidate data. An area calculation part is configured to calculate an overlap area between a first pattern in the contour data acquired by the first acquisition part and a second pattern in the contour data acquired by the second acquisition part, based on the superimposed data, for each of the plurality of layout candidate data.
    Type: Application
    Filed: April 23, 2015
    Publication date: August 18, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi MORISAKI, Satoshi Usui
  • Publication number: 20150379185
    Abstract: According to one embodiment, there is provided a mask data generation method. The mask data generation method includes obtaining depth information about a pattern depth of a hole included in design information about a semiconductor device. The mask data generation method includes obtaining a first correction rule used to correct, in terms of the pattern depth, a process conversion difference between a resist pattern and a processed pattern. The mask data generation method includes determining temporary mask data including a lithography target pattern by applying a first process conversion difference correction processing to a dimension of hole pattern arranged in design layout data based on the depth information and the first correction rule.
    Type: Application
    Filed: September 4, 2014
    Publication date: December 31, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi MORISAKI, Satoshi USUI, Katsuhiro ISHIDA