Abstract: A speaker includes a main-cone and a sub-cone. Linear thin portions configured to reduce a plate thickness of the sub-cone are formed on a region containing at least any one of an outer side and an inner side of the sub-cone. Each of the linear thin portions has both of a component in a radial direction and a component in a circumferential direction of the sub-cone. First and second linear thin portions cross each other at an intersection. With this configuration, stiffness of the whole sub-cone is reduced to enhance a divided vibration of the sub-cone. In particular, a vibrational displacement of an outer peripheral portion of the sub-cone, from which a sound is mainly radiated, is increased.

Abstract: A speaker includes a main-cone and a sub-cone. Linear thin portions configured to reduce a plate thickness of the sub-cone are formed on a region containing at least any one of an outer side and an inner side of the sub-cone. Each of the linear thin portions has both of a component in a radial direction and a component in a circumferential direction of the sub-cone. The linear thin portion and the linear thin portion cross each other at an intersection. With this configuration, stiffness of the whole sub-cone is reduced to enhance a divided vibration of the sub-cone. In particular, a vibrational displacement of an outer peripheral portion of the sub-cone, from which a sound is mainly radiated, is increased.

Abstract: A signal processing circuit has two types of filters: an IIR filter 11 and an FIR filter 12 having an equivalent transfer function at all times. In an adjustment mode in which the signal processing circuit is adjusted to have an arbitrary transfer function, the signal processing circuit makes a configuration setting to use the IIR filter 11. When completing the adjustment or in a signal processing mode, the signal processing circuit makes a configuration setting change to switch to the FIR filter 12 having the equivalent transfer function.

Abstract: A signal receiving apparatus 2 has a memory circuit 22, writing of data contained in a digital input signal transmitted from a signal transmitting apparatus 1 is performed using a clock signal separated and created by a PLL circuit 21 from the digital input signal received, and reading is performed using a reference clock signal with quartz accuracy from a reference clock generating circuit 24. To reproduce the digital input signal by correcting the shift between the clock signal and the reference clock signal, the signal receiving apparatus detects the shift between the two clock signals. When the signal receiving apparatus 2 side lags behind the signal transmitting apparatus 1, the data contained in the digital input signal undergoes thinning out, and when it leads, a signal generated from previous and subsequent digital input signal is interpolated.

Abstract: A band-splitting time compensation signal processing device 2 includes a band-splitting circuit 211 for extracting, after extracting a signal of a high-frequency band component or low-frequency band component from an input signal, a signal of the low-frequency band component or high-frequency band component by subtracting the signal of the high-frequency band component or low-frequency band component from the input signal; a delay circuit 212 for delaying, for adjusting arrival time, at least one of the high-frequency band component and low-frequency band component output from the band-splitting circuit 211; and a mixing circuit 213 for combining the high-frequency band component or low-frequency band component output from the delay circuit 212 with the low-frequency band component or high-frequency band component output from the band-splitting circuit 211.

Abstract: A complementary pulse width modulation circuit is composed of a signal generating circuit 10 for generating first and second pulse width modulation signals (PWM#1 and PWM#2) that are complementary to each other from an input signal (IN) in response to a sampling synchronous signal (Sample) generated in synchronization with a clock (CLK); and a signal output circuit 20 for combining a positive signal and a negative signal of the first pulse width modulation signal (PWM#1) generated by the signal generating circuit, and for combining the first pulse width modulation signal (PWM#1) combined with the second pulse width modulation signal (PWM#2), followed by outputting.

Abstract: A complementary pulse width modulation circuit is composed of a signal generating circuit 10 for generating first and second pulse width modulation signals (PWM#1 and PWM#2) that are complementary to each other from an input signal (IN) in response to a sampling synchronous signal (Sample) generated in synchronization with a clock (CLK); and a signal output circuit 20 for combining a positive signal and a negative signal of the first pulse width modulation signal (PWM#1) generated by the signal generating circuit, and for combining the first pulse width modulation signal (PWM#1) combined with the second pulse width modulation signal (PWM#2), followed by outputting.

Abstract: A signal transmission device includes a transmitting circuit 11 and a receiving circuit 12 provided with shunt regulator power supplies 110 and 120 for causing fixed currents to flow thereinto respectively, and a signal transmission path 13 connecting between the transmitting circuit 11 and the receiving circuit 12 and having a function of preventing an alternating current component, in which a ground GNDA of the transmitting circuit 11 and a ground GNDB of the receiving circuit 12 are disposed independently of each other, and are connected to a ground GNDC of the shunt regulator power supplies 110 and 120 at a single point.

Abstract: A signal transmission device 10 is constructed in such a way that transmitting equipment 11 and receiving equipment 12 are connected to each other via a transmission path which consists of at least hot and cold signal lines, and a signal output stage of the transmitting equipment 11 is comprised of a current output circuit 112 and a load impedance Z (113) for converting a current I0 created by the current output circuit 112 into a voltage, the load impedance Z (113) has an end connected to the hot signal line (H) of the transmission path 13 and another end connected to the cold signal line (C) of the transmission path, and the cold signal line (C) of the transmission path is connected to a ground terminal (GNDB) of the receiving equipment 12.

Abstract: A signal processing circuit has two types of filters: an IIR filter 11 and an FIR filter 12 having an equivalent transfer function at all times. In an adjustment mode in which the signal processing circuit is adjusted to have an arbitrary transfer function, the signal processing circuit makes a configuration setting to use the IIR filter 11. When completing the adjustment or in a signal processing mode, the signal processing circuit makes a configuration setting change to switch to the FIR filter 12 having the equivalent transfer function.

Abstract: A signal receiving apparatus 2 has a memory circuit 22, writing of data contained in a digital input signal transmitted from a signal transmitting apparatus 1 is performed using a clock signal separated and created by a PLL circuit 21 from the digital input signal received, and reading is performed using a reference clock signal with quartz accuracy from a reference clock generating circuit 24. To reproduce the digital input signal by correcting the shift between the clock signal and the reference clock signal, the signal receiving apparatus detects the shift between the two clock signals. When the signal receiving apparatus 2 side lags behind the signal transmitting apparatus 1, the data contained in the digital input signal undergoes thinning out, and when it leads, a signal generated from previous and subsequent digital input signal is interpolated.

Abstract: A band-splitting time compensation signal processing device 2 includes a band-splitting circuit 211 for extracting, after extracting a signal of a high-frequency band component or low-frequency band component from an input signal, a signal of the low-frequency band component or high-frequency band component by subtracting the signal of the high-frequency band component or low-frequency band component from the input signal; a delay circuit 212 for delaying, for adjusting arrival time, at least one of the high-frequency band component and low-frequency band component output from the band-splitting circuit 211; and a mixing circuit 213 for combining the high-frequency band component or low-frequency band component output from the delay circuit 212 with the low-frequency band component or high-frequency band component output from the band-splitting circuit 211.

Abstract: A pulse modulated signal (ei) output from a pulse modulator (1) and a feedback signal (ef) containing distortion caused by a power switch (3) are integrated in a first integrator (21) and a second integrator (24), respectively, and are input to input terminals of a comparator (25 or 29), respectively, so that a correction signal (Vc) is generated.

Abstract: A motional feedback (MFB) signal control unit includes a vibration displacement calculating part which generates a vibration displacement detecting signal in response to the input of a vibration detecting signal from a vibration detecting coil of a speaker unit, a vibration speed calculating part which generates a vibration speed detecting signal in response to the input of the vibration detecting signal, a processed signal generating part which generates a feedback signal in response to the input of the vibration displacement signal and the vibration speed detecting signal, and an adder which adds the feedback signal to a sound signal outputted from a sound reproducing unit so as to input the sound signal to a driving voice coil of the speaker unit.

Abstract: A pulse modulated signal (ei) output from a pulse modulator (1) and a feedback signal (ef) containing distortion caused by a power switch (3) are integrated in a first integrator (21) and a second integrator (24), respectively, and are input to input terminals of a comparator (25 or 29), respectively, so that a correction signal (Vc) is generated.

Abstract: A pulse modulated signal (ei) output from a pulse modulator (1) and a feedback signal (ef) containing distortion caused by a power switch (3) are integrated in a first integrator (21) and a second integrator (24), respectively, and are input to input terminals of a comparator (25 or 29), respectively, so that a correction signal (Vc) is generated.

Abstract: A pulse modulated signal (ei) output from a pulse modulator (1) and a feedback signal (ef) containing distortion caused by a power switch (3) are integrated in a first integrator (21) and a second integrator (24), respectively, and are input to input terminals of a comparator (25 or 29), respectively, so that a correction signal (Vc) is generated.

Abstract: A pulse modulated signal (ei) output from a pulse modulator (1) and a feedback signal (ef) containing distortion caused by a power switch (3) are integrated in a first integrator (21) and a second integrator (24), respectively, and are input to input terminals of a comparator (25 or 29), respectively, so that a correction signal (Vc) is generated.

Abstract: A damper-mounting wall portion 40 which is provided on a small-diameter end of a trumpet-shape part of a frame 1 so as to extend in a diametrically inward direction is formed with an outside diameter which is larger than a diameter of a damper 8 which is adhered thereto. On a peripheral edge portion of the damper-mounting wall portion 40, there is integrally formed an annular eave-shaped barrier wall portion 41 which extends in an axial direction toward the front side of the frame 1 so as to enclose the circumference of the damper 8 at a position away from the periphery of the damper 8.

Abstract: A pulse modulated signal (ei) output from a pulse modulator (1) and a feedback signal (ef) containing distortion caused by a power switch (3) are integrated in a first integrator (21) and a second integrator (24), respectively, and are input to input terminals of a comparator (25 or 29), respectively, so that a correction signal (Vc) is generated.