Patents by Inventor Tsuyoshi Nishiwaki
Tsuyoshi Nishiwaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240079460Abstract: A semiconductor device includes a first electrode, a second electrode located on the first electrode, a semiconductor part located between the first electrode and the second electrode, a first interconnect located between the semiconductor part and the second electrode, a third electrode located in the semiconductor part and separated from the semiconductor part, a fourth electrode located lower than the third electrode in the semiconductor part, a first plug connecting the second electrode to the fourth electrode, and a second plug. The third electrode includes a ring portion, and an extension portion extending from the ring portion into an interior of the ring portion. The fourth electrode is located in the interior of the ring portion in a plane perpendicular to a vertical direction. The fourth electrode is separated from the semiconductor part. The second plug connects the first interconnect to the extension portion.Type: ApplicationFiled: December 8, 2022Publication date: March 7, 2024Inventors: Hiroaki KATOU, Katsura MIYASHITA, Saya SHIMOMURA, Tsuyoshi KACHI, Tatsuya NISHIWAKI
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Publication number: 20230125063Abstract: A semiconductor device includes a semiconductor substrate and a metal film. The metal film is located on the semiconductor substrate. The metal film includes a portion to have a Schottky junction with the semiconductor substrate. The metal film is made of an aluminum alloy in which an element is added to aluminum. The metal film includes a lower metal layer and an upper metal layer. The lower metal layer is located on the semiconductor substrate. The upper metal layer stacks on the lower metal layer. The lower metal layer has a thickness of 2.6 micrometers or less in a stacking direction of the lower metal layer and the upper metal layer.Type: ApplicationFiled: December 14, 2022Publication date: April 20, 2023Inventors: Seiji NOMA, Tomofusa SHIGA, Kouji SENDA, Tsuyoshi NISHIWAKI, Yuta FURUMURA, Akitaka SOENO
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Patent number: 11617416Abstract: An upper of a shoe covering at least a part of a foot, the upper including: a medial portion covering a medial surface of the foot; a lateral portion covering a lateral surface of the foot; a plurality of panel portions provided in the medial portion and/or the lateral portion while being spaced apart from each other in a front-rear direction of the foot and extending in a foot girth direction crossing the front-rear direction of the foot; and a plurality of string portions formed from linear members extending in the front-rear direction, and arranged so as to extend between a pair of the plurality of panel portions that are adjacent to each other in the front-rear direction, wherein the panel portion and the string portion are formed from a single piece of fabric.Type: GrantFiled: March 20, 2017Date of Patent: April 4, 2023Assignee: ASICS CORPORATIONInventors: Tsuyoshi Nishiwaki, Shingo Takashima, Hisanori Fujita, Kenta Moriyasu
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Publication number: 20230037426Abstract: A mouth cover includes a mouth cover body that covers at least the mouth and the nostrils of a wearer, and wearing portions that are connected to the mouth cover body and allow the wearer to wear the mouth cover body. The mouth cover body includes an opening in a downward direction from a position directly facing the mouth of the wearer.Type: ApplicationFiled: October 21, 2022Publication date: February 9, 2023Inventors: MAKOTO FUKUDA, TSUYOSHI NISHIWAKI, YOSUKE OTSUKA, TAKEHIRO TAGAWA, KENICHI HARANO, JUN KONDO, KOICHI MONMA, MIZUHO IRIE, KEI KANEMATSU
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Publication number: 20220149190Abstract: A semiconductor device includes: a semiconductor substrate; a trench gate portion on the semiconductor substrate; a surface electrode covering an upper side of the semiconductor substrate; and an interlayer insulating film insulating the trench gate portion from the surface electrode. The semiconductor substrate includes: a drift region; a body region above the drift region; a barrier region below at least a part of the body region; and a pillar region extending from the surface of the semiconductor substrate to the barrier region and in Schottky contact with the surface electrode. The interlayer insulating film has an acute angle between a top surface and a side surface thereof.Type: ApplicationFiled: January 25, 2022Publication date: May 12, 2022Inventors: Satoshi KUWANO, Tsuyoshi NISHIWAKI, Yuta FURUMURA
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Patent number: 11058170Abstract: There is provided a footwear capable of efficiently removing vibrations of specific frequencies that could propagate to the human body upon landing during running or walking. A footwear includes a sole; an upper connected to an upper-side perimeter region of the sole; and a vibration absorbing unit which absorbs vibration generated by an impact upon landing. The vibration absorbing unit includes a platy flexible support portion which has a smaller rigidity in the vertical direction than in the horizontal direction, and a weight portion provided in the support portion. The support portion is fixed to the sole or the upper, surrounding a perimeter of the weight portion.Type: GrantFiled: December 28, 2015Date of Patent: July 13, 2021Inventors: Tsuyoshi Nishiwaki, Sho Takamasu, Koki Matsuo, Yutaro Iwasa, Shigeyuki Mitsui, Katsunori Yagyu
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Publication number: 20200029655Abstract: An upper of a shoe covering at least a part of a foot, the upper including: a medial portion covering a medial surface of the foot; a lateral portion covering a lateral surface of the foot; a plurality of panel portions provided in the medial portion and/or the lateral portion while being spaced apart from each other in a front-rear direction of the foot and extending in a foot girth direction crossing the front-rear direction of the foot; and a plurality of string portions formed from linear members extending in the front-rear direction, and arranged so as to extend between a pair of the plurality of panel portions that are adjacent to each other in the front-rear direction, wherein the panel portion and the string portion are formed from a single piece of fabric.Type: ApplicationFiled: March 20, 2017Publication date: January 30, 2020Applicant: ASICS CORPORATIONInventors: Tsuyoshi NISHIWAKI, Shingo TAKASHIMA, Hisanori FUJITA, Kenta MORIYASU
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Patent number: 10165830Abstract: An upper including: a plurality of panels provided in a medial side portion and/or a lateral side portion, the panels being separated from one another in a longitudinal direction of a foot, covering at least a portion of the side surface of the foot, and being pulled by a fastening member toward a center portion between the medial side and the lateral side of the foot; and a plurality of string-like non-stretchable string portions that are extending in the longitudinal direction, the string portions placed between a pair of the plurality of panels that are adjacent to each other in the longitudinal direction.Type: GrantFiled: May 29, 2014Date of Patent: January 1, 2019Assignee: ASICS CORPORATIONInventors: Tsuyoshi Nishiwaki, Shingo Takashima, Hisanori Fujita, Yoshinori Fujita
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Publication number: 20180368514Abstract: There is provided a footwear capable of efficiently removing vibrations of specific frequencies that could propagate to the human body upon landing during running or walking. A footwear includes a sole; an upper connected to an upper-side perimeter region of the sole; and a vibration absorbing unit which absorbs vibration generated by an impact upon landing. The vibration absorbing unit includes a platy flexible support portion which has a smaller rigidity in the vertical direction than in the horizontal direction, and a weight portion provided in the support portion. The support portion is fixed to the sole or the upper, surrounding a perimeter of the weight portion.Type: ApplicationFiled: December 28, 2015Publication date: December 27, 2018Inventors: TSUYOSHI NISHIWAKI, SHO TAKAMASU, KOKI MATSUO, YUTARO IWASA, SHIGEYUKI MITSUI, KATSUNORI YAGYU
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Patent number: 10153168Abstract: A method of manufacturing a semiconductor device includes: forming a light absorbing layer on a front surface of a semiconductor substrate or in the semiconductor substrate; forming a high concentration layer, in which an impurity concentration is increased, by implanting impurities into the semiconductor substrate; and heating the high concentration layer so as to activate the impurities in the high concentration layer. The formation of the light absorbing layer and the formation of the high concentration layer are performed such that the light absorbing layer and the high concentration layer at least partially overlap each other. The high concentration layer is heated by irradiating the high concentration layer with light from a front surface side of the semiconductor substrate in the heating of the high concentration layer.Type: GrantFiled: November 9, 2017Date of Patent: December 11, 2018Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Tsuyoshi Nishiwaki
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Patent number: 10074648Abstract: A method of manufacturing a semiconductor device includes: implanting charged particles into a first range and a second range in a semiconductor substrate from at least one of a first surface of the semiconductor substrate and a second surface of the semiconductor substrate located on an opposite side of the first surface so as to increase crystal defect densities in the first range and the second range; implanting n-type impurities into the first range from the first surface so as to make a region amorphous, the region being in the first range and disposed at the first surface; irradiating the first surface with first laser after the implantation of the charged particles and the implantation of the n-type impurities so as to heat the first range and the second range; and crystallizing the region which has been made amorphous in or after the irradiation of the first laser.Type: GrantFiled: September 28, 2017Date of Patent: September 11, 2018Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Hiroshi Hosokawa, Shinya Iwasaki, Tsuyoshi Nishiwaki, Atsushi Imai, Shuhei Oki
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Publication number: 20180182625Abstract: A method of manufacturing a semiconductor device includes: forming a light absorbing layer on a front surface of a semiconductor substrate or in the semiconductor substrate; forming a high concentration layer, in which an impurity concentration is increased, by implanting impurities into the semiconductor substrate; and heating the high concentration layer so as to activate the impurities in the high concentration layer. The formation of the light absorbing layer and the formation of the high concentration layer are performed such that the light absorbing layer and the high concentration layer at least partially overlap each other. The high concentration layer is heated by irradiating the high concentration layer with light from a front surface side of the semiconductor substrate in the heating of the high concentration layer.Type: ApplicationFiled: November 9, 2017Publication date: June 28, 2018Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Tsuyoshi NISHIWAKI
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Publication number: 20180138170Abstract: A method of manufacturing a semiconductor device includes: implanting charged particles into a first range and a second range in a semiconductor substrate from at least one of a first surface of the semiconductor substrate and a second surface of the semiconductor substrate located on an opposite side of the first surface so as to increase crystal defect densities in the first range and the second range; implanting n-type impurities into the first range from the first surface so as to make a region amorphous, the region being in the first range and disposed at the first surface; irradiating the first surface with first laser after the implantation of the charged particles and the implantation of the n-type impurities so as to heat the first range and the second range; and crystallizing the region which has been made amorphous in or after the irradiation of the first laser.Type: ApplicationFiled: September 28, 2017Publication date: May 17, 2018Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Hiroshi HOSOKAWA, Shinya IWASAKI, Tsuyoshi NISHIWAKI, Atsushi IMAI, Shuhei OKI
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Patent number: 9763493Abstract: A mid sole arranged on an outsole having a tread surface, the mid sole including: an upper layer and a lower layer, wherein one of the upper layer and the lower layer includes a layer of a first foamed body having a thermoplastic resin component; in another one of the upper layer and the lower layer, one or two or more of a majority of a flat area of a front foot portion, a majority of a flat area of a middle foot portion, and a majority of a flat area of a rear foot portion includes a layer of a second foamed body having a thermoplastic resin component; and the second foamed body has a greater specific gravity than the first foamed body, and is formed by a low-resilience material having a low speed of recovering to its original shape after being deformed.Type: GrantFiled: March 15, 2013Date of Patent: September 19, 2017Assignee: ASICS CORPORATIONInventors: Tsuyoshi Nishiwaki, Masashi Isobe
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Publication number: 20170215523Abstract: An upper including: a plurality of panels provided in a medial side portion and/or a lateral side portion, the panels being separated from one another in a longitudinal direction of a foot, covering at least a portion of the side surface of the foot, and being pulled by a fastening member toward a center portion between the medial side and the lateral side of the foot; and a plurality of string-like non-stretchable string portions that are extending in the longitudinal direction, the string portions placed between a pair of the plurality of panels that are adjacent to each other in the longitudinal direction.Type: ApplicationFiled: May 29, 2014Publication date: August 3, 2017Applicant: ASICS CORPORATIONInventors: Tsuyoshi Nishiwaki, Shingo Takashima, Hisanori Fujita, Yoshinori Fujita
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Patent number: 9691870Abstract: A semiconductor device including a semiconductor substrate and an electrode formed from an alloy containing aluminum, silicon and titanium. The silicon content in the electrode is from 0.5 to 1.0% by weight relative to the total weight of the electrode, the titanium content in the electrode is from 0.8 to 3.0% by weight relative to the total weight of the electrode, and the thickness of the electrode is at least 1 ?m.Type: GrantFiled: December 4, 2015Date of Patent: June 27, 2017Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Takashi Ushijima, Tsuyoshi Nishiwaki, Masakazu Okada
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Publication number: 20170150782Abstract: An outsole of a shoe includes: a plurality of ridges having a tread surface to be in contact with a road surface; and at least one longitudinal groove defined between the plurality of ridges. At least in a partial area of each of a forefoot portion and a rear foot portion on a medial side of a foot, the plurality of ridges and the longitudinal groove extend in a longitudinal direction or a diagonal longitudinal direction and are set so that an angle of the ridges and that of the longitudinal groove with respect to a long axis of the outsole are in a range of 0° to 35°. A ratio of a length of the tread surface of the ridges with respect to a width of the tread surface is set to be 1.8 to 200. The width of the tread surface of the ridges is set to be greater than a width of the longitudinal groove by a factor of 2 to 100.Type: ApplicationFiled: May 14, 2014Publication date: June 1, 2017Applicant: ASICS CORPORATIONInventors: Kenta Moriyasu, Tsuyoshi Nishiwaki, Kazuo Hokkirigawa, Takeshi Yamaguchi, Kei Shibata
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Patent number: 9601592Abstract: An IGBT has an emitter region, a top body region that is formed below the emitter region, a floating region that is formed below the top body region, a bottom body region that is formed below the floating region, a trench, a gate insulating film that covers an inner face of the trench, and a gate electrode that is arranged inside the trench. When a distribution of a concentration of p-type impurities in the top body region and the floating region, which are located below the emitter region, is viewed along a thickness direction of a semiconductor substrate, the concentration of the p-type impurities decreases as a downward distance increases from an upper end of the top body region that is located below the emitter region, and assumes a local minimum value at a predetermined depth in the floating region.Type: GrantFiled: October 15, 2015Date of Patent: March 21, 2017Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Masaru Senoo, Kyosuke Miyagi, Tsuyoshi Nishiwaki, Jun Saito
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Patent number: 9530859Abstract: A manufacturing method for a semiconductor device including a drift layer; a body layer contacting a front surface of the drift layer; an emitter layer provided on a portion of a front surface of the body layer and exposed on the front surface of the substrate; a buffer layer contacting a back surface of the drift layer; a collector layer contacting a back surface of the buffer layer and exposed on a back surface of the substrate; and a gate electrode facing, via an insulator, the body layer in an area where the body layer separates the emitter layer from the drift layer, includes preparing a wafer that includes a first layer, and a second layer layered on a back surface of the first layer and having a higher polycrystalline silicon concentration than the first layer, and forming the buffer layer by implanting and diffusing ions in the second layer.Type: GrantFiled: November 21, 2013Date of Patent: December 27, 2016Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Shuhei Oki, Tsuyoshi Nishiwaki
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Publication number: 20160163812Abstract: A semiconductor device including a semiconductor substrate and an electrode formed from an alloy containing aluminum, silicon and titanium. The silicon content in the electrode is from 0.5 to 1.0% by weight relative to the total weight of the electrode, the titanium content in the electrode is from 0.8 to 3.0% by weight relative to the total weight of the electrode, and the thickness of the electrode is at least 1 ?m.Type: ApplicationFiled: December 4, 2015Publication date: June 9, 2016Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Takashi USHIJIMA, Tsuyoshi NISHIWAKI, Masakazu OKADA