Patents by Inventor Tsuyoshi Nishiwaki

Tsuyoshi Nishiwaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10688787
    Abstract: Provided is an ink jet recording method capable of suppressing deterioration in an ejection property when voltage control of a recording head is performed. The ink jet recording method includes using an ink jet recording apparatus having a recording head equipped with a heater, a first protection layer and a second protection layer made of a metal material, and a unit of applying a voltage with the second protection layer as a cathode and an ink-mediated conduction site as an anode and ejecting the ink from the recording head to record an image on a recording medium, wherein the ink is an aqueous ink containing a component having an anionic group and a soluble metal ion having a standard electrode potential of more than 0 V.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: June 23, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventors: Mamiko Kaji, Satoshi Takebayashi, Yuko Nishiwaki, Tsuyoshi Kanke, Takashi Imai
  • Patent number: 10564371
    Abstract: A waveguide sheet captures incident light and waveguides the incident light in a direction intersecting with an incident direction. The waveguide sheet includes a diffraction grating layer that changes a traveling direction of the incident light and a plurality of first light-transmissive pairs. Each of the first light-transmissive pairs includes a first light-transmissive layer having a shape with first concave streaks and first convex streaks being repeatedly arranged in a first direction that is a direction intersecting with the incident direction, and a second light-transmissive layer laminated on the first light-transmissive layer.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: February 18, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Seiji Nishiwaki, Tohru Nakagawa, Tsuyoshi Yamamoto
  • Publication number: 20200029655
    Abstract: An upper of a shoe covering at least a part of a foot, the upper including: a medial portion covering a medial surface of the foot; a lateral portion covering a lateral surface of the foot; a plurality of panel portions provided in the medial portion and/or the lateral portion while being spaced apart from each other in a front-rear direction of the foot and extending in a foot girth direction crossing the front-rear direction of the foot; and a plurality of string portions formed from linear members extending in the front-rear direction, and arranged so as to extend between a pair of the plurality of panel portions that are adjacent to each other in the front-rear direction, wherein the panel portion and the string portion are formed from a single piece of fabric.
    Type: Application
    Filed: March 20, 2017
    Publication date: January 30, 2020
    Applicant: ASICS CORPORATION
    Inventors: Tsuyoshi NISHIWAKI, Shingo TAKASHIMA, Hisanori FUJITA, Kenta MORIYASU
  • Publication number: 20190293880
    Abstract: A waveguide sheet captures incident light and waveguides the incident light in a direction intersecting with an incident direction. The waveguide sheet includes a diffraction grating layer that changes a traveling direction of the incident light and a plurality of first light-transmissive pairs. Each of the first light-transmissive pairs includes a first light-transmissive layer having a shape with first concave streaks and first convex streaks being repeatedly arranged in a first direction that is a direction intersecting with the incident direction, and a second light-transmissive layer laminated on the first light-transmissive layer.
    Type: Application
    Filed: June 11, 2019
    Publication date: September 26, 2019
    Inventors: Seiji NISHIWAKI, Tohru NAKAGAWA, Tsuyoshi YAMAMOTO
  • Patent number: 10165830
    Abstract: An upper including: a plurality of panels provided in a medial side portion and/or a lateral side portion, the panels being separated from one another in a longitudinal direction of a foot, covering at least a portion of the side surface of the foot, and being pulled by a fastening member toward a center portion between the medial side and the lateral side of the foot; and a plurality of string-like non-stretchable string portions that are extending in the longitudinal direction, the string portions placed between a pair of the plurality of panels that are adjacent to each other in the longitudinal direction.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: January 1, 2019
    Assignee: ASICS CORPORATION
    Inventors: Tsuyoshi Nishiwaki, Shingo Takashima, Hisanori Fujita, Yoshinori Fujita
  • Publication number: 20180368514
    Abstract: There is provided a footwear capable of efficiently removing vibrations of specific frequencies that could propagate to the human body upon landing during running or walking. A footwear includes a sole; an upper connected to an upper-side perimeter region of the sole; and a vibration absorbing unit which absorbs vibration generated by an impact upon landing. The vibration absorbing unit includes a platy flexible support portion which has a smaller rigidity in the vertical direction than in the horizontal direction, and a weight portion provided in the support portion. The support portion is fixed to the sole or the upper, surrounding a perimeter of the weight portion.
    Type: Application
    Filed: December 28, 2015
    Publication date: December 27, 2018
    Inventors: TSUYOSHI NISHIWAKI, SHO TAKAMASU, KOKI MATSUO, YUTARO IWASA, SHIGEYUKI MITSUI, KATSUNORI YAGYU
  • Patent number: 10153168
    Abstract: A method of manufacturing a semiconductor device includes: forming a light absorbing layer on a front surface of a semiconductor substrate or in the semiconductor substrate; forming a high concentration layer, in which an impurity concentration is increased, by implanting impurities into the semiconductor substrate; and heating the high concentration layer so as to activate the impurities in the high concentration layer. The formation of the light absorbing layer and the formation of the high concentration layer are performed such that the light absorbing layer and the high concentration layer at least partially overlap each other. The high concentration layer is heated by irradiating the high concentration layer with light from a front surface side of the semiconductor substrate in the heating of the high concentration layer.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: December 11, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Tsuyoshi Nishiwaki
  • Patent number: 10074648
    Abstract: A method of manufacturing a semiconductor device includes: implanting charged particles into a first range and a second range in a semiconductor substrate from at least one of a first surface of the semiconductor substrate and a second surface of the semiconductor substrate located on an opposite side of the first surface so as to increase crystal defect densities in the first range and the second range; implanting n-type impurities into the first range from the first surface so as to make a region amorphous, the region being in the first range and disposed at the first surface; irradiating the first surface with first laser after the implantation of the charged particles and the implantation of the n-type impurities so as to heat the first range and the second range; and crystallizing the region which has been made amorphous in or after the irradiation of the first laser.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: September 11, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hiroshi Hosokawa, Shinya Iwasaki, Tsuyoshi Nishiwaki, Atsushi Imai, Shuhei Oki
  • Publication number: 20180182625
    Abstract: A method of manufacturing a semiconductor device includes: forming a light absorbing layer on a front surface of a semiconductor substrate or in the semiconductor substrate; forming a high concentration layer, in which an impurity concentration is increased, by implanting impurities into the semiconductor substrate; and heating the high concentration layer so as to activate the impurities in the high concentration layer. The formation of the light absorbing layer and the formation of the high concentration layer are performed such that the light absorbing layer and the high concentration layer at least partially overlap each other. The high concentration layer is heated by irradiating the high concentration layer with light from a front surface side of the semiconductor substrate in the heating of the high concentration layer.
    Type: Application
    Filed: November 9, 2017
    Publication date: June 28, 2018
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Tsuyoshi NISHIWAKI
  • Publication number: 20180138170
    Abstract: A method of manufacturing a semiconductor device includes: implanting charged particles into a first range and a second range in a semiconductor substrate from at least one of a first surface of the semiconductor substrate and a second surface of the semiconductor substrate located on an opposite side of the first surface so as to increase crystal defect densities in the first range and the second range; implanting n-type impurities into the first range from the first surface so as to make a region amorphous, the region being in the first range and disposed at the first surface; irradiating the first surface with first laser after the implantation of the charged particles and the implantation of the n-type impurities so as to heat the first range and the second range; and crystallizing the region which has been made amorphous in or after the irradiation of the first laser.
    Type: Application
    Filed: September 28, 2017
    Publication date: May 17, 2018
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hiroshi HOSOKAWA, Shinya IWASAKI, Tsuyoshi NISHIWAKI, Atsushi IMAI, Shuhei OKI
  • Patent number: 9763493
    Abstract: A mid sole arranged on an outsole having a tread surface, the mid sole including: an upper layer and a lower layer, wherein one of the upper layer and the lower layer includes a layer of a first foamed body having a thermoplastic resin component; in another one of the upper layer and the lower layer, one or two or more of a majority of a flat area of a front foot portion, a majority of a flat area of a middle foot portion, and a majority of a flat area of a rear foot portion includes a layer of a second foamed body having a thermoplastic resin component; and the second foamed body has a greater specific gravity than the first foamed body, and is formed by a low-resilience material having a low speed of recovering to its original shape after being deformed.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 19, 2017
    Assignee: ASICS CORPORATION
    Inventors: Tsuyoshi Nishiwaki, Masashi Isobe
  • Publication number: 20170215523
    Abstract: An upper including: a plurality of panels provided in a medial side portion and/or a lateral side portion, the panels being separated from one another in a longitudinal direction of a foot, covering at least a portion of the side surface of the foot, and being pulled by a fastening member toward a center portion between the medial side and the lateral side of the foot; and a plurality of string-like non-stretchable string portions that are extending in the longitudinal direction, the string portions placed between a pair of the plurality of panels that are adjacent to each other in the longitudinal direction.
    Type: Application
    Filed: May 29, 2014
    Publication date: August 3, 2017
    Applicant: ASICS CORPORATION
    Inventors: Tsuyoshi Nishiwaki, Shingo Takashima, Hisanori Fujita, Yoshinori Fujita
  • Patent number: 9691870
    Abstract: A semiconductor device including a semiconductor substrate and an electrode formed from an alloy containing aluminum, silicon and titanium. The silicon content in the electrode is from 0.5 to 1.0% by weight relative to the total weight of the electrode, the titanium content in the electrode is from 0.8 to 3.0% by weight relative to the total weight of the electrode, and the thickness of the electrode is at least 1 ?m.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: June 27, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takashi Ushijima, Tsuyoshi Nishiwaki, Masakazu Okada
  • Publication number: 20170150782
    Abstract: An outsole of a shoe includes: a plurality of ridges having a tread surface to be in contact with a road surface; and at least one longitudinal groove defined between the plurality of ridges. At least in a partial area of each of a forefoot portion and a rear foot portion on a medial side of a foot, the plurality of ridges and the longitudinal groove extend in a longitudinal direction or a diagonal longitudinal direction and are set so that an angle of the ridges and that of the longitudinal groove with respect to a long axis of the outsole are in a range of 0° to 35°. A ratio of a length of the tread surface of the ridges with respect to a width of the tread surface is set to be 1.8 to 200. The width of the tread surface of the ridges is set to be greater than a width of the longitudinal groove by a factor of 2 to 100.
    Type: Application
    Filed: May 14, 2014
    Publication date: June 1, 2017
    Applicant: ASICS CORPORATION
    Inventors: Kenta Moriyasu, Tsuyoshi Nishiwaki, Kazuo Hokkirigawa, Takeshi Yamaguchi, Kei Shibata
  • Patent number: 9601592
    Abstract: An IGBT has an emitter region, a top body region that is formed below the emitter region, a floating region that is formed below the top body region, a bottom body region that is formed below the floating region, a trench, a gate insulating film that covers an inner face of the trench, and a gate electrode that is arranged inside the trench. When a distribution of a concentration of p-type impurities in the top body region and the floating region, which are located below the emitter region, is viewed along a thickness direction of a semiconductor substrate, the concentration of the p-type impurities decreases as a downward distance increases from an upper end of the top body region that is located below the emitter region, and assumes a local minimum value at a predetermined depth in the floating region.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: March 21, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Masaru Senoo, Kyosuke Miyagi, Tsuyoshi Nishiwaki, Jun Saito
  • Patent number: 9530859
    Abstract: A manufacturing method for a semiconductor device including a drift layer; a body layer contacting a front surface of the drift layer; an emitter layer provided on a portion of a front surface of the body layer and exposed on the front surface of the substrate; a buffer layer contacting a back surface of the drift layer; a collector layer contacting a back surface of the buffer layer and exposed on a back surface of the substrate; and a gate electrode facing, via an insulator, the body layer in an area where the body layer separates the emitter layer from the drift layer, includes preparing a wafer that includes a first layer, and a second layer layered on a back surface of the first layer and having a higher polycrystalline silicon concentration than the first layer, and forming the buffer layer by implanting and diffusing ions in the second layer.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: December 27, 2016
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Shuhei Oki, Tsuyoshi Nishiwaki
  • Publication number: 20160163812
    Abstract: A semiconductor device including a semiconductor substrate and an electrode formed from an alloy containing aluminum, silicon and titanium. The silicon content in the electrode is from 0.5 to 1.0% by weight relative to the total weight of the electrode, the titanium content in the electrode is from 0.8 to 3.0% by weight relative to the total weight of the electrode, and the thickness of the electrode is at least 1 ?m.
    Type: Application
    Filed: December 4, 2015
    Publication date: June 9, 2016
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takashi USHIJIMA, Tsuyoshi NISHIWAKI, Masakazu OKADA
  • Publication number: 20160100654
    Abstract: A shoe including a sole 1 for absorbing an impact of landing, an upper 2 for wrapping around an instep, and shoelace means 3 for fitting the upper 2 to the instep, the upper 2 including: a main portion 2M covering a medial side surface, a lateral side surface, a toe, the instep and a back surface of a foot; a side edge portion having a plurality of first eyelets H1; a first side panel 51 covering the medial side surface of the foot; and a second side panel 52 covering the lateral side surface of the foot, wherein each side panel includes: a tip portion 53 having a second eyelet H2 which is provided at a tip of the side panel and which the shoelace means passes through and engages with; a bottom portion 54 attached to the main portion and/or the sole; and a middle portion 55 arranged between the tip portion and the bottom portion so as to allow the tip portion to move in the front-back direction of the foot with respect to the bottom portion, wherein with at least one of the side panels, the middle portion 55
    Type: Application
    Filed: December 18, 2015
    Publication date: April 14, 2016
    Applicant: ASICS CORPORATION
    Inventors: Tsuyoshi Nishiwaki, Seigo Nakaya, Tomoko Ikezawa, Moe Nagata, Kenta Moriyasu
  • Patent number: 9259054
    Abstract: A low rigidity region being more stretchable and bendable than a high rigidity region, includes a main portion, and a medial first flexible portion and a lateral first flexible portion extending from the main portion in the medial and lateral directions. The main portion covers a portion of the area from the shaft of the first proximal phalanx to the shaft of the second proximal phalanx, the medial first flexible portion covers a portion of the area from the shaft of the first proximal phalanx to the head of the first metatarsal bone, and the lateral first flexible portion extends to the lateral side of the foot from the main portion. When pushing off the foot onto the medial/lateral side in a diagonally forward direction, the upper bends along the diagonal bend lines. Therefore, the diagonal portions and the main portion serve as the bend lines.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 16, 2016
    Assignee: ASICS Corporation
    Inventors: Tsuyoshi Nishiwaki, Kouki Matsuo, Kenta Moriyasu, Seiji Yano, Rena Furuishi
  • Publication number: 20160035859
    Abstract: An IGBT has an emitter region, a top body region that is formed below the emitter region, a floating region that is formed below the top body region, a bottom body region that is formed below the floating region, a trench, a gate insulating film that covers an inner face of the trench, and a gate electrode that is arranged inside the trench. When a distribution of a concentration of p-type impurities in the top body region and the floating region, which are located below the emitter region, is viewed along a thickness direction of a semiconductor substrate, the concentration of the p-type impurities decreases as a downward distance increases from an upper end of the top body region that is located below the emitter region, and assumes a local minimum value at a predetermined depth in the floating region.
    Type: Application
    Filed: October 15, 2015
    Publication date: February 4, 2016
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Masaru SENOO, Kyosuke MIYAGI, Tsuyoshi NISHIWAKI, Jun SAITO