Patents by Inventor Tsuyoshi Ohno

Tsuyoshi Ohno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8778205
    Abstract: The present invention is a processing method including a processing step of performing predetermined processing for a workpiece; an unnecessary portion removal step of removing an unnecessary portion produced on a surface of the workpiece due to the predetermined processing; and a surface structure evaluation step of evaluating a surface structure of the workpiece from which the unnecessary portion has been removed by the unnecessary portion removal step.
    Type: Grant
    Filed: October 14, 2009
    Date of Patent: July 15, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Tsuyoshi Ohno, Toshihiko Kikuchi, Machi Moriya, Yoshitaka Saita
  • Patent number: 8085335
    Abstract: An image pickup apparatus includes an image-pickup optical system, three color separation prisms separating incident light guided by the image-pickup optical system into three-primary-color light components and emitting the light components, and three image pickup elements respectively receiving the three light components from the prisms so as to produce respective image signals. Of the three prisms, a first prism that first receives the incident light has an edge extending parallel to an incidence plane. The image-pickup optical system has a plate-like fixed aperture stop disposed between the first prism and a final lens, disposed closest to the first prism, of multiple lenses included in the image-pickup optical system. The fixed aperture stop has an aperture that limits the incident light. An edge section of the aperture has projections and depressions arranged at least in parallel to the edge, as viewed from an optical-axis direction of the final lens.
    Type: Grant
    Filed: December 15, 2008
    Date of Patent: December 27, 2011
    Assignee: Sony Corporation
    Inventors: Tsuyoshi Ohno, Hitoshi Nakanishi, Toshiaki Edamitsu
  • Publication number: 20100133231
    Abstract: The present invention is a processing method including a processing step of performing predetermined processing for a workpiece; an unnecessary portion removal step of removing an unnecessary portion produced on a surface of the workpiece due to the predetermined processing; and a surface structure evaluation step of evaluating a surface structure of the workpiece from which the unnecessary portion has been removed by the unnecessary portion removal step.
    Type: Application
    Filed: October 14, 2009
    Publication date: June 3, 2010
    Inventors: Tsuyoshi Ohno, Toshihiko Kikuchi, Machi Moriya, Yoshitaka Saita
  • Publication number: 20090185065
    Abstract: An image pickup apparatus includes an image-pickup optical system, three color separation prisms separating incident light guided by the image-pickup optical system into three-primary-color light components and emitting the light components, and three image pickup elements respectively receiving the three light components from the prisms so as to produce respective image signals. Of the three prisms, a first prism that first receives the incident light has an edge extending parallel to an incidence plane. The image-pickup optical system has a plate-like fixed aperture stop disposed between the first prism and a final lens, disposed closest to the first prism, of multiple lenses included in the image-pickup optical system. The fixed aperture stop has an aperture that limits the incident light. An edge section of the aperture has projections and depressions arranged at least in parallel to the edge, as viewed from an optical-axis direction of the final lens.
    Type: Application
    Filed: December 15, 2008
    Publication date: July 23, 2009
    Applicant: Sony Corporation
    Inventors: Tsuyoshi Ohno, Hitoshi Nakanishi, Toshiaki Edamitsu
  • Publication number: 20070132876
    Abstract: A color separation image pickup optical system is which can spectralize light with low noise and can be formed in a minimized size. The color separation image pickup optical system includes a solid-state image pickup device which in turn includes a semiconductor substrate, a plurality of photoelectric conversion elements formed on the semiconductor substrate, a transparent seal member, an a package in which the semiconductor substrate is sealed with the transparent seal member. A color light absorbing member of a single performance is disposed on the transparent seal member side with respect to the photoelectric conversion elements in the package and absorbs color light in a particular visible wavelength region with regard to the photoelectric conversion elements.
    Type: Application
    Filed: December 11, 2006
    Publication date: June 14, 2007
    Inventors: Tsuyoshi Ohno, Masaki Tamura, Hitoshi Nakanishi
  • Patent number: 6847120
    Abstract: A flip chip semiconductor device has a cell forming layer assigned to macro-cells and input and output cells and a pad forming layer assigned to power supply pads for the macro-cells and input and output cells and signal pads for the input and output cells, and the signal pads are arranged outside of the power supply pads, whereby a package substrate to be assembled with the flip chip semiconductor device is simplified by virtue of the signal lines on a level with the signal pads, because any power supply pad is not an obstacle against the signal lines.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: January 25, 2005
    Assignee: NEC Electronics Corporation
    Inventor: Tsuyoshi Ohno
  • Publication number: 20040260420
    Abstract: The present invention is a processing method including a processing step of performing predetermined processing for a workpiece; an unnecessary portion removal step of removing an unnecessary portion produced on a surface of the workpiece due to the predetermined processing; and a surface structure evaluation step of evaluating a surface structure of the workpiece from which the unnecessary portion has been removed by the unnecessary portion removal step.
    Type: Application
    Filed: June 18, 2004
    Publication date: December 23, 2004
    Applicant: Tokyo Electron Limited.
    Inventors: Tsuyoshi Ohno, Toshihiko Kikuchi, Machi Moriya, Yoshitaka Saita
  • Patent number: 6828820
    Abstract: A method for producing a stable control signal for impedance matching is provided which is capable of suppressing variation in impedance matching data by adding a shift voltage to a voltage to be compared. A comparator compares the voltage to be compared with a reference voltage and an up-down counter performs a counting operation according to a result from the comparison. A code converting circuit converts a count value output from the up-down counter to a thermometer code used for changing an impedance of an impedance varying circuit. A change in the impedance is made in a manner that, even when the voltage to be compared gets closest to the reference voltage, a shift voltage for the comparator to make an exact comparison is fed to the voltage to be compared. An averaging circuit averages a count value and the code converting circuit converts a resulting average value to the thermometer code.
    Type: Grant
    Filed: May 8, 2003
    Date of Patent: December 7, 2004
    Assignee: NEC Electronics Corporation
    Inventor: Tsuyoshi Ohno
  • Publication number: 20040021481
    Abstract: A method for producing a stable control signal for impedance matching is provided which is capable of suppressing variation in impedance matching data by adding a shift voltage to a voltage to be compared. A comparator compares the voltage to be compared with a reference voltage and an up-down counter performs a counting operation according to a result from the comparison. A code converting circuit converts a count value output from the up-down counter to a thermometer code used for changing an impedance of an impedance varying circuit. A change in the impedance is made in a manner that, even when the voltage to be compared gets closest to the reference voltage, a shift voltage for the comparator to make an exact comparison is fed to the voltage to be compared. An averaging circuit averages a count value and the code converting circuit converts a resulting average value to the thermometer code.
    Type: Application
    Filed: May 8, 2003
    Publication date: February 5, 2004
    Applicant: NEC Electronics Corporation
    Inventor: Tsuyoshi Ohno
  • Patent number: 6601225
    Abstract: In a semiconductor device including an internal circuit provided in an internal circuit area; input/output blocks provided in input/output areas surrounding the internal circuit area, each of the input/output blocks being connected by first conductive layer to the internal circuit; and pads provided in outer areas of the input/output areas, each of the pads being connected by a second conductive layer to one of the input/output blocks, the configuration of each of the input/output blocks being definite regardless of the pitch of the pads, the number of rows of the input/output blocks in the input/output areas is changed in accordance with the pitch of the pads.
    Type: Grant
    Filed: July 5, 2001
    Date of Patent: July 29, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Tsuyoshi Ohno
  • Patent number: 6489815
    Abstract: A low-noise buffer circuit stabilizing the output voltage and current to prevent noise, includes current sources connected between the CMOS circuit and power supply sources providing a power supply for the CMOS circuit, a resistor element connected to the current sources and in parallel with the CMOS circuit, the resistor element bypassing current between the current sources to prevent current fluctuation.
    Type: Grant
    Filed: April 23, 2001
    Date of Patent: December 3, 2002
    Assignee: NEC Corporation
    Inventor: Tsuyoshi Ohno
  • Publication number: 20020113319
    Abstract: A flip chip semiconductor device has a cell forming layer assigned to macro-cells and input and output cells and a pad forming layer assigned to power supply pads for the macro-cells and input and output cells and signal pads for the input and output cells, and the signal pads are arranged outside of the power supply pads, whereby a package substrate to be assembled with the flip chip semiconductor device is simplified by virtue of the signal lines on a level with the signal pads, because any power supply pad is not an obstacle against the signal lines.
    Type: Application
    Filed: December 19, 2001
    Publication date: August 22, 2002
    Inventor: Tsuyoshi Ohno
  • Patent number: 6351015
    Abstract: A MOS (Metal Oxide Semiconductor) transistor includes a gate electrode, a drain electrode, and a source electrode. The MOS transistor has an on-state resistance when the MOS transistor is in an ON state. The MOS transistor further includes a specific electrode, wherein the specific electrode connects the source electrode to a power supply section to which a power is supplied. The specific electrode has a resistance substantially identical to the on-state resistance. The specific electrode has a width substantially identical to a width of the gate electrode. The specific electrode and the gate electrode are formed at a same time.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: February 26, 2002
    Assignee: NEC Corporation
    Inventor: Tsuyoshi Ohno
  • Publication number: 20020004930
    Abstract: In a semiconductor device including an internal circuit provided in an internal circuit area; input/output blocks provided in input/output areas surrounding the internal circuit area, each of the input/output blocks being connected by first conductive layer to the internal circuit; and pads provided in outer areas of the input/output areas, each of the pads being connected by a second conductive layer to one of the input/output blocks, the configuration of each of the input/output blocks being definite regardless of the pitch of the pads, the number of rows of the input/output blocks in the input/output areas is changed in accordance with the pitch of the pads.
    Type: Application
    Filed: July 5, 2001
    Publication date: January 10, 2002
    Applicant: NEC CORPORATION
    Inventor: Tsuyoshi Ohno
  • Publication number: 20010035779
    Abstract: A low-noise buffer circuit stabilizing the output voltage and current to prevent noise, includes current sources connected between the CMOS circuit and power supply sources providing a power supply for the CMOS circuit, a resistor element connected to the current sources and in parallel with the CMOS circuit, the resistor element bypassing current between the current sources to prevent current fluctuation.
    Type: Application
    Filed: April 23, 2001
    Publication date: November 1, 2001
    Applicant: NEC CORPORATION
    Inventor: Tsuyoshi Ohno
  • Patent number: 5973544
    Abstract: An intermediate potential generating circuit mainly includes an intermediate potential generating portion and an output portion. In this event, the intermediate potential generating portion generates first and second signals having first and second intermediate potentials different from each other between a first voltage source and a second voltage source and supplies the first and second signals via first and second signal terminals. Specifically, the intermediate potential generating portion has first, second, third and fourth MOS transistors. On the other hand, the output portion supplies a power supply having a third intermediate potential between the first intermediate potential and the second intermediate potential via an output terminal and is formed by fifth and sixth MOS transistors.
    Type: Grant
    Filed: July 23, 1998
    Date of Patent: October 26, 1999
    Assignee: NEC Corporation
    Inventor: Tsuyoshi Ohno
  • Patent number: 5534785
    Abstract: An IC bare chip carrier installs an IC bare chip for performing a burn-in test and a functional examination of the bare chip. The carrier consists of an installing unit for installing the bare chip and an interconnecting unit for electrically interconnecting chip electrodes of the bare chip with output electrodes of the interconnecting unit, to be connected to apparatus for the burn-in test and the functional examination. The installing unit is made of aluminium nitride having an expansion rate near of material, ceramic, of the IC bare chip, for making fabrication of installing surface of the IC bare chip easy. The interconnecting unit has an air exchange mechanism by which the IC bare chip can be laid in a space, made by combining the installing unit and the interconnecting unit, constantly filled with inert gas such as nitrogen. The IC bare chip is transported anytime and anywhere as installed in the carrier without being contaminated.
    Type: Grant
    Filed: June 27, 1995
    Date of Patent: July 9, 1996
    Assignee: Fujitsu Limited
    Inventors: Tsutomu Yoshizaki, Shigeyuki Maruyama, Tsuyoshi Ohno
  • Patent number: 5250416
    Abstract: The present invention relates to a method for determining a slight amount of NADH or XTP which is present in a solution, with high sensitivity by the use of an NADH kinase specific for NADH by utilizing a cycling reaction, and this method permits highly sensitive determination of NADH without any influence of NAD.sup.+ and hence is useful for diagnoses of diseases and the like.
    Type: Grant
    Filed: January 21, 1992
    Date of Patent: October 5, 1993
    Assignees: Noda Institute for Scientific Rsearch, International Reagents Corp.
    Inventors: Tsuyoshi Ohno, Masaru Suzuki, Tatsuo Horiuchi, Yasushi Shirahase, Koji Kishi, Yoshifumi Watazu
  • Patent number: 5227299
    Abstract: The present invention relates to a novel NADH kinase which has high stability and is specific for NADH, and a process for producing the NADH kinase by culturing a yeast belonging to the genus Pichia in a culture medium, and this enzyme permits highly sensitive determination of NADH alone and hence is useful in the field of clinical medicine.
    Type: Grant
    Filed: January 21, 1992
    Date of Patent: July 13, 1993
    Assignee: Noda Institute for Scientific Research
    Inventors: Tsuyoshi Ohno, Masaru Suzuki, Tatsuo Horiuchi