Patents by Inventor Tsuyoshi Ohno
Tsuyoshi Ohno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8778205Abstract: The present invention is a processing method including a processing step of performing predetermined processing for a workpiece; an unnecessary portion removal step of removing an unnecessary portion produced on a surface of the workpiece due to the predetermined processing; and a surface structure evaluation step of evaluating a surface structure of the workpiece from which the unnecessary portion has been removed by the unnecessary portion removal step.Type: GrantFiled: October 14, 2009Date of Patent: July 15, 2014Assignee: Tokyo Electron LimitedInventors: Tsuyoshi Ohno, Toshihiko Kikuchi, Machi Moriya, Yoshitaka Saita
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Patent number: 8085335Abstract: An image pickup apparatus includes an image-pickup optical system, three color separation prisms separating incident light guided by the image-pickup optical system into three-primary-color light components and emitting the light components, and three image pickup elements respectively receiving the three light components from the prisms so as to produce respective image signals. Of the three prisms, a first prism that first receives the incident light has an edge extending parallel to an incidence plane. The image-pickup optical system has a plate-like fixed aperture stop disposed between the first prism and a final lens, disposed closest to the first prism, of multiple lenses included in the image-pickup optical system. The fixed aperture stop has an aperture that limits the incident light. An edge section of the aperture has projections and depressions arranged at least in parallel to the edge, as viewed from an optical-axis direction of the final lens.Type: GrantFiled: December 15, 2008Date of Patent: December 27, 2011Assignee: Sony CorporationInventors: Tsuyoshi Ohno, Hitoshi Nakanishi, Toshiaki Edamitsu
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Publication number: 20100133231Abstract: The present invention is a processing method including a processing step of performing predetermined processing for a workpiece; an unnecessary portion removal step of removing an unnecessary portion produced on a surface of the workpiece due to the predetermined processing; and a surface structure evaluation step of evaluating a surface structure of the workpiece from which the unnecessary portion has been removed by the unnecessary portion removal step.Type: ApplicationFiled: October 14, 2009Publication date: June 3, 2010Inventors: Tsuyoshi Ohno, Toshihiko Kikuchi, Machi Moriya, Yoshitaka Saita
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Publication number: 20090185065Abstract: An image pickup apparatus includes an image-pickup optical system, three color separation prisms separating incident light guided by the image-pickup optical system into three-primary-color light components and emitting the light components, and three image pickup elements respectively receiving the three light components from the prisms so as to produce respective image signals. Of the three prisms, a first prism that first receives the incident light has an edge extending parallel to an incidence plane. The image-pickup optical system has a plate-like fixed aperture stop disposed between the first prism and a final lens, disposed closest to the first prism, of multiple lenses included in the image-pickup optical system. The fixed aperture stop has an aperture that limits the incident light. An edge section of the aperture has projections and depressions arranged at least in parallel to the edge, as viewed from an optical-axis direction of the final lens.Type: ApplicationFiled: December 15, 2008Publication date: July 23, 2009Applicant: Sony CorporationInventors: Tsuyoshi Ohno, Hitoshi Nakanishi, Toshiaki Edamitsu
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Publication number: 20070132876Abstract: A color separation image pickup optical system is which can spectralize light with low noise and can be formed in a minimized size. The color separation image pickup optical system includes a solid-state image pickup device which in turn includes a semiconductor substrate, a plurality of photoelectric conversion elements formed on the semiconductor substrate, a transparent seal member, an a package in which the semiconductor substrate is sealed with the transparent seal member. A color light absorbing member of a single performance is disposed on the transparent seal member side with respect to the photoelectric conversion elements in the package and absorbs color light in a particular visible wavelength region with regard to the photoelectric conversion elements.Type: ApplicationFiled: December 11, 2006Publication date: June 14, 2007Inventors: Tsuyoshi Ohno, Masaki Tamura, Hitoshi Nakanishi
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Patent number: 6847120Abstract: A flip chip semiconductor device has a cell forming layer assigned to macro-cells and input and output cells and a pad forming layer assigned to power supply pads for the macro-cells and input and output cells and signal pads for the input and output cells, and the signal pads are arranged outside of the power supply pads, whereby a package substrate to be assembled with the flip chip semiconductor device is simplified by virtue of the signal lines on a level with the signal pads, because any power supply pad is not an obstacle against the signal lines.Type: GrantFiled: December 18, 2001Date of Patent: January 25, 2005Assignee: NEC Electronics CorporationInventor: Tsuyoshi Ohno
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Publication number: 20040260420Abstract: The present invention is a processing method including a processing step of performing predetermined processing for a workpiece; an unnecessary portion removal step of removing an unnecessary portion produced on a surface of the workpiece due to the predetermined processing; and a surface structure evaluation step of evaluating a surface structure of the workpiece from which the unnecessary portion has been removed by the unnecessary portion removal step.Type: ApplicationFiled: June 18, 2004Publication date: December 23, 2004Applicant: Tokyo Electron Limited.Inventors: Tsuyoshi Ohno, Toshihiko Kikuchi, Machi Moriya, Yoshitaka Saita
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Patent number: 6828820Abstract: A method for producing a stable control signal for impedance matching is provided which is capable of suppressing variation in impedance matching data by adding a shift voltage to a voltage to be compared. A comparator compares the voltage to be compared with a reference voltage and an up-down counter performs a counting operation according to a result from the comparison. A code converting circuit converts a count value output from the up-down counter to a thermometer code used for changing an impedance of an impedance varying circuit. A change in the impedance is made in a manner that, even when the voltage to be compared gets closest to the reference voltage, a shift voltage for the comparator to make an exact comparison is fed to the voltage to be compared. An averaging circuit averages a count value and the code converting circuit converts a resulting average value to the thermometer code.Type: GrantFiled: May 8, 2003Date of Patent: December 7, 2004Assignee: NEC Electronics CorporationInventor: Tsuyoshi Ohno
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Publication number: 20040021481Abstract: A method for producing a stable control signal for impedance matching is provided which is capable of suppressing variation in impedance matching data by adding a shift voltage to a voltage to be compared. A comparator compares the voltage to be compared with a reference voltage and an up-down counter performs a counting operation according to a result from the comparison. A code converting circuit converts a count value output from the up-down counter to a thermometer code used for changing an impedance of an impedance varying circuit. A change in the impedance is made in a manner that, even when the voltage to be compared gets closest to the reference voltage, a shift voltage for the comparator to make an exact comparison is fed to the voltage to be compared. An averaging circuit averages a count value and the code converting circuit converts a resulting average value to the thermometer code.Type: ApplicationFiled: May 8, 2003Publication date: February 5, 2004Applicant: NEC Electronics CorporationInventor: Tsuyoshi Ohno
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Patent number: 6601225Abstract: In a semiconductor device including an internal circuit provided in an internal circuit area; input/output blocks provided in input/output areas surrounding the internal circuit area, each of the input/output blocks being connected by first conductive layer to the internal circuit; and pads provided in outer areas of the input/output areas, each of the pads being connected by a second conductive layer to one of the input/output blocks, the configuration of each of the input/output blocks being definite regardless of the pitch of the pads, the number of rows of the input/output blocks in the input/output areas is changed in accordance with the pitch of the pads.Type: GrantFiled: July 5, 2001Date of Patent: July 29, 2003Assignee: NEC Electronics CorporationInventor: Tsuyoshi Ohno
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Patent number: 6489815Abstract: A low-noise buffer circuit stabilizing the output voltage and current to prevent noise, includes current sources connected between the CMOS circuit and power supply sources providing a power supply for the CMOS circuit, a resistor element connected to the current sources and in parallel with the CMOS circuit, the resistor element bypassing current between the current sources to prevent current fluctuation.Type: GrantFiled: April 23, 2001Date of Patent: December 3, 2002Assignee: NEC CorporationInventor: Tsuyoshi Ohno
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Publication number: 20020113319Abstract: A flip chip semiconductor device has a cell forming layer assigned to macro-cells and input and output cells and a pad forming layer assigned to power supply pads for the macro-cells and input and output cells and signal pads for the input and output cells, and the signal pads are arranged outside of the power supply pads, whereby a package substrate to be assembled with the flip chip semiconductor device is simplified by virtue of the signal lines on a level with the signal pads, because any power supply pad is not an obstacle against the signal lines.Type: ApplicationFiled: December 19, 2001Publication date: August 22, 2002Inventor: Tsuyoshi Ohno
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Patent number: 6351015Abstract: A MOS (Metal Oxide Semiconductor) transistor includes a gate electrode, a drain electrode, and a source electrode. The MOS transistor has an on-state resistance when the MOS transistor is in an ON state. The MOS transistor further includes a specific electrode, wherein the specific electrode connects the source electrode to a power supply section to which a power is supplied. The specific electrode has a resistance substantially identical to the on-state resistance. The specific electrode has a width substantially identical to a width of the gate electrode. The specific electrode and the gate electrode are formed at a same time.Type: GrantFiled: December 30, 1999Date of Patent: February 26, 2002Assignee: NEC CorporationInventor: Tsuyoshi Ohno
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Publication number: 20020004930Abstract: In a semiconductor device including an internal circuit provided in an internal circuit area; input/output blocks provided in input/output areas surrounding the internal circuit area, each of the input/output blocks being connected by first conductive layer to the internal circuit; and pads provided in outer areas of the input/output areas, each of the pads being connected by a second conductive layer to one of the input/output blocks, the configuration of each of the input/output blocks being definite regardless of the pitch of the pads, the number of rows of the input/output blocks in the input/output areas is changed in accordance with the pitch of the pads.Type: ApplicationFiled: July 5, 2001Publication date: January 10, 2002Applicant: NEC CORPORATIONInventor: Tsuyoshi Ohno
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Publication number: 20010035779Abstract: A low-noise buffer circuit stabilizing the output voltage and current to prevent noise, includes current sources connected between the CMOS circuit and power supply sources providing a power supply for the CMOS circuit, a resistor element connected to the current sources and in parallel with the CMOS circuit, the resistor element bypassing current between the current sources to prevent current fluctuation.Type: ApplicationFiled: April 23, 2001Publication date: November 1, 2001Applicant: NEC CORPORATIONInventor: Tsuyoshi Ohno
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Patent number: 5973544Abstract: An intermediate potential generating circuit mainly includes an intermediate potential generating portion and an output portion. In this event, the intermediate potential generating portion generates first and second signals having first and second intermediate potentials different from each other between a first voltage source and a second voltage source and supplies the first and second signals via first and second signal terminals. Specifically, the intermediate potential generating portion has first, second, third and fourth MOS transistors. On the other hand, the output portion supplies a power supply having a third intermediate potential between the first intermediate potential and the second intermediate potential via an output terminal and is formed by fifth and sixth MOS transistors.Type: GrantFiled: July 23, 1998Date of Patent: October 26, 1999Assignee: NEC CorporationInventor: Tsuyoshi Ohno
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Patent number: 5534785Abstract: An IC bare chip carrier installs an IC bare chip for performing a burn-in test and a functional examination of the bare chip. The carrier consists of an installing unit for installing the bare chip and an interconnecting unit for electrically interconnecting chip electrodes of the bare chip with output electrodes of the interconnecting unit, to be connected to apparatus for the burn-in test and the functional examination. The installing unit is made of aluminium nitride having an expansion rate near of material, ceramic, of the IC bare chip, for making fabrication of installing surface of the IC bare chip easy. The interconnecting unit has an air exchange mechanism by which the IC bare chip can be laid in a space, made by combining the installing unit and the interconnecting unit, constantly filled with inert gas such as nitrogen. The IC bare chip is transported anytime and anywhere as installed in the carrier without being contaminated.Type: GrantFiled: June 27, 1995Date of Patent: July 9, 1996Assignee: Fujitsu LimitedInventors: Tsutomu Yoshizaki, Shigeyuki Maruyama, Tsuyoshi Ohno
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Patent number: 5250416Abstract: The present invention relates to a method for determining a slight amount of NADH or XTP which is present in a solution, with high sensitivity by the use of an NADH kinase specific for NADH by utilizing a cycling reaction, and this method permits highly sensitive determination of NADH without any influence of NAD.sup.+ and hence is useful for diagnoses of diseases and the like.Type: GrantFiled: January 21, 1992Date of Patent: October 5, 1993Assignees: Noda Institute for Scientific Rsearch, International Reagents Corp.Inventors: Tsuyoshi Ohno, Masaru Suzuki, Tatsuo Horiuchi, Yasushi Shirahase, Koji Kishi, Yoshifumi Watazu
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Patent number: 5227299Abstract: The present invention relates to a novel NADH kinase which has high stability and is specific for NADH, and a process for producing the NADH kinase by culturing a yeast belonging to the genus Pichia in a culture medium, and this enzyme permits highly sensitive determination of NADH alone and hence is useful in the field of clinical medicine.Type: GrantFiled: January 21, 1992Date of Patent: July 13, 1993Assignee: Noda Institute for Scientific ResearchInventors: Tsuyoshi Ohno, Masaru Suzuki, Tatsuo Horiuchi