Abstract: A positive electrode mixture including a positive electrode active material represented by the following formula (1); and a solid electrolyte that comprises Li and S: aLi2MnO3bLiNi1-yM1yO2-cLiM2vM3wM4xO2??(1) wherein M1 is one or more elements selected from Co, Mn, Al, Fe, Cu, V, Zn and Cr; M2, M3 and M4 are independently one or more elements selected from Ni, Co, Mn, Al, Fe, Cu, V, Zn and Cr; M2, M3 and M4 are elements different from each other; a, b and c satisfy a+b+c=1, 0<a<1, 0<b<1 and 0<c<1; y satisfies 0?y?1; and v, w and x satisfy v+w+x=1, and satisfy 0?v?1, 0?w?1 and 0?x?1.

Abstract: A cell protection system includes a charge control MOSFET 21, a charge current detection MOSFET 23, a discharge control MOSFET 20, a discharge current detection MOSFET 22, a charge current detection resistance 19, a discharge current detection resistance 16 and a control circuit. The MOSFET 23 has a drain and a gate common with the MOSFET 21. The MOSFET 20 has a drain common with the MOSFET 21. The MOSFET 22 has a drain and a gate common with the MOSFET 20. The resistances 19 and 16 are provided in correspondence to the MOSFETs 23 and 22, respectively. The control circuit generates a gate control signal for the MOSFETs 21 and 23 by using the resistance 19 and generates a gate control signal for the MOSFETs 20 and 22 by using the resistance 16.

Abstract: A cell protection system includes a charge control MOSFET, a charge current detection MOSFET, a discharge control MOSFET, a discharge current detection MOSFET, a charge current detection resistance, a discharge current detection resistance and a control circuit. The charge current detection MOSFET has a drain and a gate common with the charge control MOSFET. The discharge control MOSFET has a drain common with the charge control MOSFET. The discharge current detection MOSFET has a drain and a gate common with the discharge control MOSFET. The resistancesare provided in correspondence to the charge and discharge current detection MOSFETs. The control circuit generates a gate control signal for the charge control and current detection MOSFETs by using one of the resistances and generates a gate control signal for the discharge control and current detection MOSFETs 20 by using another one of the resistances.

Abstract: A semiconductor device includes a first electrode, a second electrode, a first semiconductor region that is formed between the first electrode and the second electrode and is in contact with the first electrode, a second semiconductor region that is formed between the first semiconductor region and the second electrode, a contact region that is formed between the second semiconductor region and the second electrode and is in contact with the second semiconductor region and the second electrode, a plurality of third semiconductor regions that are formed between the second electrode and the first semiconductor region and are in contact with the second electrode, and a wiring that is in contact with the second electrode, a portion of the wiring bonded to the second electrode being positioned above the third semiconductor region and not positioned above the contact region.

Abstract: A semiconductor device includes first and second electrodes. First semiconductor regions of a first conductivity type are positioned between the first electrode and the second electrode and contact the first electrode. These semiconductor regions are arranged along a first direction. A second semiconductor region of the first conductivity type also contacts the first electrode and is disposed around the plurality of first semiconductor regions. The second semiconductor region has a dopant concentration that is higher than the first semiconductor regions. A semiconductor layer of a second conductivity type has portions that are between the first semiconductor regions and the second semiconductor region. These portions are in Schottky contact with the first electrode.

Abstract: A positive electrode mixture including a positive electrode active material represented by the following formula (1); and a solid electrolyte that comprises Li and S: aLi2MnO3bLiNi1-yM1yO2-cLiM2vM3wM4xO2 ??(1) wherein M1 is one or more elements selected from Co, Mn, Al, Fe, Cu, V, Zn and Cr; M2, M3 and M4 are independently one or more elements selected from Ni, Co, Mn, Al, Fe, Cu, V, Zn and Cr; M2, M3 and M4 are elements different from each other; a, b and c satisfy a+b+c=1, 0<a<1, 0<b<1 and 0<c<1; y satisfies 0?y?1; and v, w and x satisfy v+w+x=1, and satisfy 0?v?1, 0?w?1 and 0?x?1.

Abstract: Glass includes an aggregate of solid electrolyte particles including Li, P, and S, wherein when a Raman spectrum of the glass is repeatedly measured and a peak at 330 to 450 cm?1 in each Raman spectrum is separated to waveforms of individual components, a standard deviation of a waveform area ratio of each component is less than 4.0.

Abstract: A first MOSFET is formed in a first region of a chip, and a second MOSFET is formed in a second region thereof. A first source terminal and a first gate terminal are formed in the first region. In the second region, a second source terminal and a second gate terminal are arranged so as to be aligned substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned. A temperature detection diode is arranged between the first source terminal and the second source terminal. A first terminal and a second terminal of the temperature detection diode are aligned in a first direction substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned or in a second direction substantially perpendicular thereto.

Abstract: Glass includes an aggregate of solid electrolyte particles including Li, P, and S, wherein when a Raman spectrum of the glass is repeatedly measured and a peak at 330 to 450 cm?1 in each Raman spectrum is separated to waveforms of individual components, a standard deviation of a waveform area ratio of each component is less than 4.0.

Abstract: A first MOSFET is formed in a first region of a chip, and a second MOSFET is formed in a second region thereof. A first source terminal and a first gate terminal are formed in the first region. In the second region, a second source terminal and a second gate terminal are arranged so as to be aligned substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned. A temperature detection diode is arranged between the first source terminal and the second source terminal. A first terminal and a second terminal of the temperature detection diode are aligned in a first direction substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned or in a second direction substantially perpendicular thereto.

Abstract: A semiconductor device includes first and second electrodes. First semiconductor regions of a first conductivity type are positioned between the first electrode and the second electrode and contact the first electrode. These semiconductor regions are arranged along a first direction. A second semiconductor region of the first conductivity type also contacts the first electrode and is disposed around the plurality of first semiconductor regions. The second semiconductor region has a dopant concentration that is higher than the first semiconductor regions. A semiconductor layer of a second conductivity type has portions that are between the first semiconductor regions and the second semiconductor region. These portions are in Schottky contact with the first electrode.

Abstract: A battery management method and apparatus. In one embodiment of the method, a source current is divided into Ic and Icr. Ic is transmitted to and charges a battery. A first voltage is generated that is related to Icr. The first voltage is converted into a first digital signal. A processing unit receives and processes the first digital signal in accordance with instructions stored in a memory. The transmission of Ic to the battery is interrupted in response to the processing unit processing the first digital signal. Current provided by the battery is divided into Idc and Idcr. Idc is transmitted to a device. A second voltage is generated that is related to Idcr. The second voltage is converted into a second digital signal. The processing unit receives and processes the second digital signal in accordance with instructions stored in the memory. The transmission of Idc to the battery is interrupted in response to the processing unit processing the second digital signal.

Abstract: A solid electrolyte including an alkali metal element, phosphorous, sulfur and halogen as constituent components.

Abstract: A cell protection system includes a charge control MOSFET 21, a charge current detection MOSFET 23, a discharge control MOSFET 20, a discharge current detection MOSFET 22, a charge current detection resistance 19, a discharge current detection resistance 16 and a control circuit. The MOSFET 23 has a drain and a gate common with the MOSFET 21. The MOSFET 20 has a drain common with the MOSFET 21. The MOSFET 22 has a drain and a gate common with the MOSFET 20. The resistances 19 and 16 are provided in correspondence to the MOSFETs 23 and 22, respectively. The control circuit generates a gate control signal for the MOSFETs 21 and 23 by using the resistance 19 and generates a gate control signal for the MOSFETs 20 and 22 by using the resistance 16.

Abstract: A first MOSFET is formed in a first region of a chip, and a second MOSFET is formed in a second region thereof. A first source terminal and a first gate terminal are formed in the first region. In the second region, a second source terminal and a second gate terminal are arranged so as to be aligned substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned. A temperature detection diode is arranged between the first source terminal and the second source terminal. A first terminal and a second terminal of the temperature detection diode are aligned in a first direction substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned or in a second direction substantially perpendicular thereto.

Abstract: The present invention provides an optical semiconductor sealing material comprising a radically polymerized polymer of a methacrylate ester having an alicyclic hydrocarbon group containing 7 or more carbon atoms, e.g. an adamantyl group, a norbornyl group, or a dicyclopentanyl group; and an optical semiconductor sealing material comprising a radically polymerized polymer of 50 to 97 mass % of the methacrylate ester and 3 to 50 mass % of acrylate ester having a hydroxyl group. The optical semiconductor sealing material of the present invention is highly transparent and stable to UV light and thus does not undergo yellowing. In addition, the material exhibits excellent compatibility between heat resistance and refractive index, does not undergo deformation or cracking during heating processes such as reflow soldering, and shows high processability.

Abstract: According to one embodiment, in a semiconductor device, a semiconductor laminated body includes a first semiconductor region of a first conductivity type and a second semiconductor region of the first conductivity type provided on the first semiconductor region and having a higher concentration of impurities than that of the first semiconductor region. A third semiconductor region includes a side surface and a lower end, the side surface and the lower end are surrounded by the semiconductor laminated body. A fourth semiconductor region of a second conductivity type is provided between the semiconductor laminated body and the third semiconductor region. A fifth semiconductor region of the first conductivity type is in contact with an outside surface of the semiconductor laminated body opposite to an inside surface of the semiconductor laminated body, the inside surface is in contact with the fourth semiconductor region.

Abstract: In one embodiment of the cold end switch battery management control method, a battery generates an output voltage at a positive terminal thereof. A first control voltage is also generated by an integrated circuit. A gate of a field effect transistor (FET) receives the first control voltage, wherein the FET comprises a drain and a source with the source coupled to a negative terminal of the battery. The FET transmits current towards the battery in response to the gate receiving the first control voltage, wherein the first control voltage is greater than the output voltage, and wherein the first control voltage is less than a breakdown voltage of the integrated circuit.

Abstract: A composite material including a conducting material and an alkali metal sulfide formed integrally on the surface of the conducting material.

Abstract: According to one embodiment, a semiconductor device includes, a drain, source, base and drift regions, a gate electrode, a gate insulating film, a first semiconductor region, a drain electrode, and a source electrode. The drain region has a first portion, and a second portion having a surface extending in a first direction which is vertical to a main surface of the first portion. The source region extends in a second direction which is parallel to the second portion, and is provided to be spaced from the drain region. The gate electrode extends in the first direction and a third direction which is vertical to the first direction and the second direction, and passes through the base region in the third direction. The first semiconductor region is provided between the gate insulating film and the drain region, and has a lower impurity concentration than the drift region.