Patents by Inventor Tsuyoshi Sugisaki
Tsuyoshi Sugisaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240032297Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnect layers, first and second memory pillars, and a plurality of first plugs. The plurality of first interconnect layers include a first array region where the first memory pillar penetrates the plurality of first interconnect layers, a second array region where the second memory pillar penetrates the plurality of first interconnect layers, and a coupling region where a plurality of coupling parts respectively coupled to the plurality of first plugs are formed. Along a first direction parallel to the semiconductor substrate, the first array region, the coupling region, and the second array region are arranged in order.Type: ApplicationFiled: September 27, 2023Publication date: January 25, 2024Applicant: KIOXIA CORPORATIONInventors: Go OIKE, Tsuyoshi SUGISAKI
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Publication number: 20230402322Abstract: A semiconductor device according to an embodiment includes a first conductor, a first oxide semiconductor, a first insulator, a second conductor, a third conductor, and a fourth conductor. The first oxide semiconductor contacts, at one end, the first conductor, and extends in a first direction intersecting a surface of the first conductor. The first insulator surrounds a side surface of the first oxide semiconductor. The second conductor and the first oxide semiconductor interpose the first insulator therebetween. The third conductor contacts another end of the first oxide semiconductor. The fourth conductor extends in a second direction intersecting the first direction, and contacts a second conductor on a side opposite to the first insulator. The second conductor is of a material with a higher work function than a material of the fourth conductor.Type: ApplicationFiled: March 13, 2023Publication date: December 14, 2023Applicant: Kioxia CorporationInventors: Shoichi Kabuyanagi, Tsuyoshi Sugisaki, Shosuke Fujii
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Patent number: 11818890Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnect layers, first and second memory pillars, and a plurality of first plugs. The plurality of first interconnect layers include a first array region where the first memory pillar penetrates the plurality of first interconnect layers, a second array region where the second memory pillar penetrates the plurality of first interconnect layers, and a coupling region where a plurality of coupling parts respectively coupled to the plurality of first plugs are formed. Along a first direction parallel to the semiconductor substrate, the first array region, the coupling region, and the second array region are arranged in order.Type: GrantFiled: February 7, 2022Date of Patent: November 14, 2023Assignee: KIOXIA CORPORATIONInventors: Go Oike, Tsuyoshi Sugisaki
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Patent number: 11729975Abstract: A semiconductor memory includes a stack section comprising a first area including a plurality of first conductors and a plurality of first insulators alternately stacked in a first direction and memory cells, and a second area including respective end portions of the plurality of stacked first conductors and the plurality of stacked first insulators, a plurality of contact plugs respectively reaching the plurality of first conductors in the second area, first and second supporting portions configured respectively to pass through the stack section in the first direction and arranged in a second direction, which crosses the first direction, in the second area, and a layer between respective adjacent first insulators, among the plurality of first insulators that are stacked, between the first supporting portion and the second supporting portion, wherein the layer is made of a material that is different from that of the first conductors.Type: GrantFiled: April 1, 2021Date of Patent: August 15, 2023Assignee: Kioxia CorporationInventor: Tsuyoshi Sugisaki
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Publication number: 20220157851Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnect layers, first and second memory pillars, and a plurality of first plugs. The plurality of first interconnect layers include a first array region where the first memory pillar penetrates the plurality of first interconnect layers, a second array region where the second memory pillar penetrates the plurality of first interconnect layers, and a coupling region where a plurality of coupling parts respectively coupled to the plurality of first plugs are formed. Along a first direction parallel to the semiconductor substrate, the first array region, the coupling region, and the second array region are arranged in order.Type: ApplicationFiled: February 7, 2022Publication date: May 19, 2022Applicant: KIOXIA CORPORATIONInventors: Go OIKE, Tsuyoshi SUGISAKI
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Patent number: 11282858Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnect layers, first and second memory pillars, and a plurality of first plugs. The plurality of first interconnect layers include a first array region where the first memory pillar penetrates the plurality of first interconnect layers, a second array region where the second memory pillar penetrates the plurality of first interconnect layers, and a coupling region where a plurality of coupling parts respectively coupled to the plurality of first plugs are formed. Along a first direction parallel to the semiconductor substrate, the first array region, the coupling region, and the second array region are arranged in order.Type: GrantFiled: November 3, 2020Date of Patent: March 22, 2022Assignee: KIOXIA CORPORATIONInventors: Go Oike, Tsuyoshi Sugisaki
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Publication number: 20210217774Abstract: A semiconductor memory includes a stack section comprising a first area including a plurality of first conductors and a plurality of first insulators alternately stacked in a first direction and memory cells, and a second area including respective end portions of the plurality of stacked first conductors and the plurality of stacked first insulators, a plurality of contact plugs respectively reaching the plurality of first conductors in the second area, first and second supporting portions configured respectively to pass through the stack section in the first direction and arranged in a second direction, which crosses the first direction, in the second area, and a layer between respective adjacent first insulators, among the plurality of first insulators that are stacked, between the first supporting portion and the second supporting portion, wherein the layer is made of a material that is different from that of the first conductors.Type: ApplicationFiled: April 1, 2021Publication date: July 15, 2021Inventor: Tsuyoshi SUGISAKI
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Patent number: 11049870Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a memory cell array, first circuitry and a via. The semiconductor substrate includes a first main surface and a second main surface opposite the first main surface. The memory cell array is provided on the first main surface. The memory cell array includes stacked memory cells. The first circuitry is provided on the second main surface. The first circuitry is configured to operate the memory cells. The via penetrates through the semiconductor substrate. The via provides electrical connection between the memory cells and the first circuitry.Type: GrantFiled: March 11, 2019Date of Patent: June 29, 2021Assignee: Toshiba Memory CorporationInventor: Tsuyoshi Sugisaki
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Patent number: 10998332Abstract: A semiconductor memory includes a stack section comprising a first area including a plurality of first conductors and a plurality of first insulators alternately stacked in a first direction and memory cells, and a second area including respective end portions of the plurality of stacked first conductors and the plurality of stacked first insulators, a plurality of contact plugs respectively reaching the plurality of first conductors in the second area, first and second supporting portions configured respectively to pass through the stack section in the first direction and arranged in a second direction, which crosses the first direction, in the second area, and a layer between respective adjacent first insulators, among the plurality of first insulators that are stacked, between the first supporting portion and the second supporting portion, wherein the layer is made of a material that is different from that of the first conductors.Type: GrantFiled: August 22, 2018Date of Patent: May 4, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventor: Tsuyoshi Sugisaki
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Publication number: 20210050370Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnect layers, first and second memory pillars, and a plurality of first plugs. The plurality of first interconnect layers include a first array region where the first memory pillar penetrates the plurality of first interconnect layers, a second array region where the second memory pillar penetrates the plurality of first interconnect layers, and a coupling region where a plurality of coupling parts respectively coupled to the plurality of first plugs are formed. Along a first direction parallel to the semiconductor substrate, the first array region, the coupling region, and the second array region are arranged in order.Type: ApplicationFiled: November 3, 2020Publication date: February 18, 2021Applicant: Toshiba Memory CorporationInventors: Go OIKE, Tsuyoshi SUGISAKI
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Patent number: 10861875Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnect layers, first and second memory pillars, and a plurality of first plugs. The plurality of first interconnect layers include a first array region where the first memory pillar penetrates the plurality of first interconnect layers, a second array region where the second memory pillar penetrates the plurality of first interconnect layers, and a coupling region where a plurality of coupling parts respectively coupled to the plurality of first plugs are formed. Along a first direction parallel to the semiconductor substrate, the first array region, the coupling region, and the second array region are arranged in order.Type: GrantFiled: January 24, 2020Date of Patent: December 8, 2020Assignee: Toshiba Memory CorporationInventors: Go Oike, Tsuyoshi Sugisaki
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Patent number: 10763277Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnect layers, first and second memory pillars, and a plurality of first plugs. The plurality of first interconnect layers include a first array region where the first memory pillar penetrates the plurality of first interconnect layers, a second array region where the second memory pillar penetrates the plurality of first interconnect layers, and a coupling region where a plurality of coupling parts respectively coupled to the plurality of first plugs are formed. Along a first direction parallel to the semiconductor substrate, the first array region, the coupling region, and the second array region are arranged in order.Type: GrantFiled: August 31, 2018Date of Patent: September 1, 2020Assignee: Toshiba Memory CorporationInventors: Go Oike, Tsuyoshi Sugisaki
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Publication number: 20200161333Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnect layers, first and second memory pillars, and a plurality of first plugs. The plurality of first interconnect layers include a first array region where the first memory pillar penetrates the plurality of first interconnect layers, a second array region where the second memory pillar penetrates the plurality of first interconnect layers, and a coupling region where a plurality of coupling parts respectively coupled to the plurality of first plugs are formed. Along a first direction parallel to the semiconductor substrate, the first array region, the coupling region, and the second array region are arranged in order.Type: ApplicationFiled: January 24, 2020Publication date: May 21, 2020Applicant: Toshiba Memory CorporationInventors: Go OIKE, Tsuyoshi SUGISAKI
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Publication number: 20200098776Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a memory cell array, first circuitry and a via. The semiconductor substrate includes a first main surface and a second main surface opposite the first main surface. The memory cell array is provided on the first main surface. The memory cell array includes stacked memory cells. The first circuitry is provided on the second main surface. The first circuitry is configured to operate the memory cells. The via penetrates through the semiconductor substrate. The via provides electrical connection between the memory cells and the first circuitry.Type: ApplicationFiled: March 11, 2019Publication date: March 26, 2020Applicant: Toshiba Memory CorporationInventor: Tsuyoshi SUGISAKI
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Publication number: 20190287990Abstract: A semiconductor memory includes a stack section comprising a first area including a plurality of first conductors and a plurality of first insulators alternately stacked in a first direction and memory cells, and a second area including respective end portions of the plurality of stacked first conductors and the plurality of stacked first insulators, a plurality of contact plugs respectively reaching the plurality of first conductors in the second area, first and second supporting portions configured respectively to pass through the stack section in the first direction and arranged in a second direction, which crosses the first direction, in the second area, and a layer between respective adjacent first insulators, among the plurality of first insulators that are stacked, between the first supporting portion and the second supporting portion, wherein the layer is made of a material that is different from that of the first conductors.Type: ApplicationFiled: August 22, 2018Publication date: September 19, 2019Inventor: Tsuyoshi SUGISAKI
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Publication number: 20190287995Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnect layers, first and second memory pillars, and a plurality of first plugs. The plurality of first interconnect layers include a first array region where the first memory pillar penetrates the plurality of first interconnect layers, a second array region where the second memory pillar penetrates the plurality of first interconnect layers, and a coupling region where a plurality of coupling parts respectively coupled to the plurality of first plugs are formed. Along a first direction parallel to the semiconductor substrate, the first array region, the coupling region, and the second array region are arranged in order.Type: ApplicationFiled: August 31, 2018Publication date: September 19, 2019Applicant: Toshiba Memory CorporationInventors: Go Oike, Tsuyoshi Sugisaki
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Patent number: 10381081Abstract: A memory device includes first and second electrode layers, first and second semiconductor pillars, an interconnect, and a first connecting conductor. The first and second electrode layers are stacked in a first direction. The second electrode layers are positioned in the first direction when viewed from the first electrode layers. The first semiconductor pillar extends in the first direction through the first electrode layers. The second semiconductor pillar extends in the first direction through the second electrode layers. The interconnect is provided between the first and second electrode layers, and is electrically connected to the first and second semiconductor pillars. The first connecting conductor extends in the first direction, is connected to one of the first electrode layers and one of the second electrode layers. The first connecting conductor extends in the first direction, and crosses at least one of the second electrode layers.Type: GrantFiled: March 13, 2018Date of Patent: August 13, 2019Assignee: Toshiba Memory CorporationInventors: Tsuyoshi Sugisaki, Yasuhito Nakajima
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Publication number: 20190080764Abstract: A memory device includes first and second electrode layers, first and second semiconductor pillars, an interconnect, and a first connecting conductor. The first and second electrode layers are stacked in a first direction. The second electrode layers are positioned in the first direction when viewed from the first electrode layers. The first semiconductor pillar extends in the first direction through the first electrode layers. The second semiconductor pillar extends in the first direction through the second electrode layers. The interconnect is provided between the first and second electrode layers, and is electrically connected to the first and second semiconductor pillars. The first connecting conductor extends in the first direction, is connected to one of the first electrode layers and one of the second electrode layers. The first connecting conductor extends in the first direction, and crosses at least one of the second electrode layers.Type: ApplicationFiled: March 13, 2018Publication date: March 14, 2019Applicant: Toshiba Memory CorporationInventors: Tsuyoshi Sugisaki, Yasuhito Nakajima
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Patent number: 8258600Abstract: A semiconductor device includes a capacitor element including a first comb-shaped interconnection formed over a substrate and including a first comb tooth, a second comb-shaped interconnection formed over the substrate and including a second comb tooth opposed to the first comb tooth, and a first electrode and a second electrode opposed to each other with opposed surfaces of the first electrode and the second electrode intersecting a longitudinal direction of the first comb tooth and the second comb tooth, a first dielectric layer formed between the first electrode and the second electrode, the first electrode being connected to the first comb tooth, and the second electrode being connected to the second comb tooth.Type: GrantFiled: March 9, 2010Date of Patent: September 4, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Tsuyoshi Sugisaki, Hajime Kurata
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Publication number: 20120119326Abstract: A capacitor includes first electrode patterns and second electrode patterns disposed alternately on a plane, each of the first electrode patterns having a linear shape and extending in a first direction from a first end to a third end with a first length, each of the second electrodes having a linear shape and extending in said first direction from a second end to a fourth end with a second length shorter than the first length, a first wiring pattern supplying a first voltage to the first electrode patterns by first via-plugs, and a second wiring pattern supplying a second voltage to the second electrode patterns by second via-plugs, wherein the first end of the first electrode pattern extends beyond the second end of the second electrode pattern and the third end of the first electrode pattern extends beyond the fourth end of said the electrode.Type: ApplicationFiled: August 11, 2011Publication date: May 17, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Tsuyoshi Sugisaki, Masatoshi Fukuda