Abstract: A display driver capable of implementing natural moving image display with a reduced power consumption, based on display data of following frame is generated on a cycle longer than a read cycle for display data from a built-in RAM, and a display unit and an electronic instrument having the display driver. A display driver IC with a built-in RAM stores in an FIFO memory compressed data input on a cycle longer than a drive cycle that is based on the display data, uses an MPEG decoder circuit to decompress the compressed data on a cycle substantially equivalent to the read cycle of the display data RAM to generate the display data, and writes the display data into the display data RAM prior to the read operation at a speed equal to or higher than the reading speed.

Abstract: A semiconductor device is provided for various types of interfaces for performing various types of data processing operations based on input or output compressed data, and electronic equipment. A multiplexing/demultiplexing section demultiplexes compressed data compressed according to the MPEG-4 standard, for example, from multiplexed data which is multiplexed compressed data corresponding to various types of media, and supplies the demultiplexed and compressed data to output interface ICs corresponding to each output device including a display section. The output interface ICs decompress the demultiplexed and compressed data according to the MPEG-4 standard, for example. An input interface IC compresses data input from an input device according to the MPEG-4 standard, for example. The compressed data is supplied to the multiplexing/demultiplexing section and multiplexed therein.

Abstract: A display controller has a display data RAM, and generates a frame frequency in an internal oscillating circuit. A memory area of the display data RAM corresponds to a moving image display area of a liquid crystal panel. The liquid crystal panel is driven by moving image data read from the display data RAM at the frame frequency. In the display controller, display data generated at a frame frequency lower than the frame frequency from a display data generation circuit is written to the display data RAM. In this case, a control operation is performed such that the display data is read at the frame frequency after a write operation is performed precedently by at least one scanning line.

Abstract: The objective of the invention is to provide a RAM-incorporated driver that enables the writing of moving-image data to a RAM simultaneously with the writing of still-image data to the RAM. A RAM-incorporated X-driver IC comprises first and second bus lines for transferring still-image data and moving-image data from an MPU; a RAM for storing the still-image data and moving-image data; first column and page address control circuits for specifying column and page addresses in RAM for writing still-image data; second column and page address control circuits for specifying column and page addresses in RAM for writing moving-image data; an MPU-unrelated control circuit for controlling each of the address control circuits, based on commands from the MPU; a display address control circuit for controlling the reading of still-image data and moving-image data stored in the RAM, as display data; and a driver-related control circuit for controlling the display address control circuit.

Abstract: The objective of the invention is to provide a RAM-incorporated driver that enables the writing of moving-image data to a RAM simultaneously with the writing of still-image data to a RAM, at a reduced energy consumption A RAM incorporated X-driver IC receives still-image data from an MPU and moving-image data that is input by a separate system through a high-speed serial transfer line in accordance with the LVDS standard. An LVDS reception circuit suppresses the consumption of a steady current by which the differential input receiver operates, based on a data validation signal that becomes active when transfer data on the high-speed serial data transfer line from the MPU becomes valid. The still-image data and moving-image data that is received by separate systems is written to a RAM through first and second bus lines, respectively. Reading of still-image data and moving-image data, which is stored in a RAM, as display data is controlled by a display address control circuit.

Abstract: The present invention provides an image decoding and reconstruction system for successively reading out and decoding compression video data constituting one screen page and reconstructing an image with a memory of a small capacity. The system of the invention divides an image of one screen page into 8x8-pixel blocks, compresses video data by discrete cosine transform, successively reads data in the unit of a 2×2 matrix of the 8×8-pixel blocks, and stores the video data along horizontal scanning lines in one of two memories while reading other video data previously stored along the scanning lines out of the other memory. The invention also provides an interblock distortion removal filter for eliminating interblock distortions due to orthogonal transform.

Abstract: A laminate structure includes a base material made of a resin and a laminate material made of a metal, the laminate material being laminated as one or more plating layers on one surface or on both surfaces of the base material, wherein the laminate material has a flexural modulus of elasticity larger than that of the base material and has a thickness such that a changing rate of rigidity relative to the thickness ratio of the laminate material in the total laminate structure is larger than a changing rate of weight.

Abstract: An object of the present invention is to realize the gray shading through PWM in the MLS drive method while minimizing increase of the number of voltage levels and degradation of the display characteristics. A given calculation is performed out by using a gray shades data, a virtual data generated by the gray shades data and an orthogonal function. The resulting data is then used to perform the pulse width modulation to realize the pulse width modulation of binary level in the MLS drive method. The virtual data is generated so that the sum of the number of 1 in the gray shades data and the number of 1 in the virtual data is even number. The gray shades data and virtual data are converted into data symmetrical about 0. The converted data is used with an orthogonal function to perform a matrix calculation with the result thereof being then converted into a positive integer. Alternatively, the gray shades data, virtual data and orthogonal function are used to perform a matrix calculation.

Abstract: Electrodes for electrically connecting to the outside are formed along one long side of a rectangular semiconductor chip 20. The electrodes are arranged in two rows, one of output terminals 21 and the other of input terminals 22 and power supply terminals 23, or are arranged in one row of the output terminals, input terminals and power supply terminals. Input protective resistors and static electricity protective diodes 28 for the input terminals are located outside the output terminals to be separated from the output system by at least the size of the output terminals. The external circuit connected to the output terminals 21 of the semiconductor device, for example the wiring 35 extending from the inner leads 33 of a tape carrier 29 are routed inside the electrodes toward the opposite long side of the semiconductor device, so that the wiring area overlaps the top of the semiconductor device in a plan view.

Abstract: The present invention provides an image decoding and reconstruction system for successively reading out and decoding compression video data constituting one screen page and reconstructing an image with a memory of a small capacity. The system of the invention divides an image of one screen page into 8.times.8-pixel blocks, compresses video data by discrete cosine transform, successively reads data in the unit of a 2.times.2 matrix of the 8.times.8-pixel blocks, and stores the video data along horizontal scanning lines in one of two memories while reading other video data previously stored along the scanning lines out of the other memory. The invention also provides an interblock distortion removal filter for eliminating interblock distortions due to orthogonal transform.

Abstract: A sound generation circuit for producing a dual tone which includes memory circuitry for storing data for controlling production of the dual tone, selection circuitry for selecting data stored in the memory circuitry and frequency dividers for producing an output signal having a frequency which varies based on the data selected by the selection circuitry. The production of the dual tone is based on the output signal of the frequency dividing circuitry. The sound generation circuit also includes logic circuitry to inhibit selection by the selection circuitry of data for controlling production by the sound generation circuit of a musical note when the sound generation circuit is currently producing a dual tone. The melody and dial sections of the sound generation circuit employ common elements.

Abstract: A semiconductor circuit has a logic cell comprising insulation gate type transistors wherein the structure of the cell can be easily corrected or changed improving the overall operational speed of the logic circuit produced while controlling the electrical power consumption of the circuit from being significantly increase. Input transistors and output transistors in a logic circuit layout employing the basic cell configuration of this invention are arranged at regular intervals along the power supply buses so that each channel width of the transistors is at right angles to these power wirings and the channel widths, W.sub.I (W.sub.IP, W.sub.IN), of the input transistors of the circuit are formed to be narrower than the channel widths, W.sub.O (W.sub.OP, W.sub.ON), of the output transistors of the circuit.