Patents by Inventor Tsuyoshi Tomoyama
Tsuyoshi Tomoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230363148Abstract: An apparatus includes a plurality of memory cells in a memory cell array region; a plurality of word lines extending across the memory cell array region and a peripheral region in which no memory cell is arranged; a plurality of contact plugs on even numbered ones of the plurality of word lines in the peripheral region, respectively; and a plurality of insulating walls on odd numbered ones of the plurality of word lines in the peripheral region, respectively.Type: ApplicationFiled: May 9, 2022Publication date: November 9, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: Yuki Munetaka, Tsuyoshi Tomoyama
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Patent number: 11798837Abstract: Methods for forming openings in conductive layers and using the same are described. An example method includes: forming a conductive layer; forming a first hard mask on the conductive layer; forming a second hard mask on the first hard mask; providing an opening through the first and second masks; and removing a surface of the conductive layer under the opening. The first hard mask may have hardness greater than hardness of the second hard mask.Type: GrantFiled: October 1, 2021Date of Patent: October 24, 2023Assignee: Micron Technology, Inc.Inventors: Tsuyoshi Tomoyama, Keisuke Otsuka
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Publication number: 20230200058Abstract: An apparatus includes a substrate; a memory cell region provided over the substrate; a peripheral region provided over the substrate and adjacent to the memory cell region; and a plurality of word-lines extending in parallel across the memory cell region and the peripheral region; a first insulating film covering top surfaces of the plurality of word-lines in each of the memory cell region and the peripheral region and covering side surfaces of upper portions of the plurality of word-lines in the peripheral region without covering side surfaces of the upper portions of the plurality of word-lines in the memory cell region.Type: ApplicationFiled: December 21, 2021Publication date: June 22, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: Naoyoshi Kobayashi, Tsuyoshi Tomoyama
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Publication number: 20230107365Abstract: Methods for forming openings in conductive layers and using the same are described. An example method includes: forming a conductive layer; forming a first hard mask on the conductive layer; forming a second hard mask on the first hard mask; providing an opening through the first and second masks; and removing a surface of the conductive layer under the opening. The first hard mask may have hardness greater than hardness of the second hard mask.Type: ApplicationFiled: October 1, 2021Publication date: April 6, 2023Applicant: Micron Technology, Inc.Inventors: TSUYOSHI TOMOYAMA, KEISUKE OTSUKA
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Patent number: 11056494Abstract: Some embodiments include an integrated assembly having a paired-memory-cell-region within a memory-array-region. The paired-memory-cell-region includes a bitline-contact-structure between a first charge-storage-device-contact-structure and a second charge-storage-device-contact-structure. A first insulative region is between the bitline-contact-structure and the first charge-storage-device-contact-structure. A second insulative region is between the bitline-contact-structure and the second charge-storage-device-contact-structure. The first and second insulative regions both include a first semiconductor material which is in a nonconductive configuration. A transistor gate is over a peripheral region proximate the memory-array-region. The transistor gate has a second semiconductor material which is a same semiconductor composition and thickness as the first semiconductor material, but which is in a conductive configuration. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: October 15, 2019Date of Patent: July 6, 2021Assignee: Micron Technology, Inc.Inventor: Tsuyoshi Tomoyama
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Patent number: 11037800Abstract: Some embodiments include a method of patterning a target material. An assembly is provided which has a masking material over the target material. First lines are formed over the assembly. The first lines extend along a first direction and are laterally spaced from one another by first spaces. Second lines are formed over the first lines. The second lines extend along a second direction which crosses the first direction, and are laterally spaced from one another by second spaces. The second lines cross the first lines at first crossing regions. The second spaces cross the first spaces at second crossing regions. A pattern includes the first and second crossing regions. The pattern is transferred into the masking material to form holes in the masking material in locations directly under the first and second crossing regions. The holes are extended into the target material.Type: GrantFiled: March 12, 2019Date of Patent: June 15, 2021Assignee: Micron Technology, Inc.Inventors: Tsuyoshi Tomoyama, Hiromitsu Oshima, Tomohiro Iwaki
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Publication number: 20200294814Abstract: Some embodiments include a method of patterning a target material. An assembly is provided which has a masking material over the target material. First lines are formed over the assembly. The first lines extend along a first direction and are laterally spaced from one another by first spaces. Second lines are formed over the first lines. The second lines extend along a second direction which crosses the first direction, and are laterally spaced from one another by second spaces. The second lines cross the first lines at first crossing regions. The second spaces cross the first spaces at second crossing regions. A pattern includes the first and second crossing regions. The pattern is transferred into the masking material to form holes in the masking material in locations directly under the first and second crossing regions. The holes are extended into the target material.Type: ApplicationFiled: March 12, 2019Publication date: September 17, 2020Applicant: Micron Technology, Inc.Inventors: Tsuyoshi Tomoyama, Hiromitsu Oshima, Tomohiro Iwaki
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Patent number: 10573654Abstract: Some embodiments include an integrated assembly having a paired-memory-cell-region within a memory-array-region. The paired-memory-cell-region includes a bitline-contact-structure between a first charge-storage-device-contact-structure and a second charge-storage-device-contact-structure. A first insulative region is between the bitline-contact-structure and the first charge-storage-device-contact-structure. A second insulative region is between the bitline-contact-structure and the second charge-storage-device-contact-structure. The first and second insulative regions both include a first semiconductor material which is in a nonconductive configuration. A transistor gate is over a peripheral region proximate the memory-array-region. The transistor gate has a second semiconductor material which is a same semiconductor composition and thickness as the first semiconductor material, but which is in a conductive configuration. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: June 18, 2018Date of Patent: February 25, 2020Assignee: Micron Technology, Inc.Inventor: Tsuyoshi Tomoyama
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Publication number: 20200043934Abstract: Some embodiments include an integrated assembly having a paired-memory-cell-region within a memory-array-region. The paired-memory-cell-region includes a bitline-contact-structure between a first charge-storage-device-contact-structure and a second charge-storage-device-contact-structure. A first insulative region is between the bitline-contact-structure and the first charge-storage-device-contact-structure. A second insulative region is between the bitline-contact-structure and the second charge-storage-device-contact-structure. The first and second insulative regions both include a first semiconductor material which is in a nonconductive configuration. A transistor gate is over a peripheral region proximate the memory-array-region. The transistor gate has a second semiconductor material which is a same semiconductor composition and thickness as the first semiconductor material, but which is in a conductive configuration. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: October 15, 2019Publication date: February 6, 2020Applicant: Micron Technology, Inc.Inventor: Tsuyoshi Tomoyama
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Publication number: 20190386010Abstract: Some embodiments include an integrated assembly having a paired-memory-cell-region within a memory-array-region. The paired-memory-cell-region includes a bitline-contact-structure between a first charge-storage-device-contact-structure and a second charge-storage-device-contact-structure. A first insulative region is between the bitline-contact-structure and the first charge-storage-device-contact-structure. A second insulative region is between the bitline-contact-structure and the second charge-storage-device-contact-structure. The first and second insulative regions both include a first semiconductor material which is in a nonconductive configuration. A transistor gate is over a peripheral region proximate the memory-array-region. The transistor gate has a second semiconductor material which is a same semiconductor composition and thickness as the first semiconductor material, but which is in a conductive configuration. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: June 18, 2018Publication date: December 19, 2019Applicant: Micron Technology, Inc.Inventor: Tsuyoshi Tomoyama
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Patent number: 9741723Abstract: A semiconductor device is provided, which prevents a case where the widths of word lines become uneven because of a stress developing at the border between a memory cell area and a peripheral circuit area. The semiconductor device 1 has a semiconductor substrate 2 on which a memory cell area MC defined by a peripheral isolation region 3c. The memory cell area MC has multiple cell active regions k defined by multiple cell isolation regions 3a, 3b. Guard active regions GLa, GLb made of the semiconductor substrate are disposed in the border between the memory cell area MC and the peripheral isolation region 3c to separate the memory cell isolation regions 3a, 3b from the peripheral isolation region 3c.Type: GrantFiled: September 14, 2015Date of Patent: August 22, 2017Assignee: Micron Technology, Inc.Inventor: Tsuyoshi Tomoyama
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Publication number: 20160233297Abstract: A semiconductor device is provided, which prevents a case where the widths of word lines become uneven because of a stress developing at the border between a memory cell area and a peripheral circuit area. The semiconductor device 1 has a semiconductor substrate 2 on which a memory cell area MC defined by a peripheral isolation region 3c. The memory cell area MC has multiple cell active regions k defined by multiple cell isolation regions 3a, 3b. Guard active regions GLa, GLb made of the semiconductor substrate are disposed in the border between the memory cell area MC and the peripheral isolation region 3c to separate the memory cell isolation regions 3a, 3b from the peripheral isolation region 3c.Type: ApplicationFiled: September 14, 2015Publication date: August 11, 2016Inventor: Tsuyoshi TOMOYAMA
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Publication number: 20130270677Abstract: A semiconductor device includes a semiconductor substrate having a principal surface, a first conductor formed on the semiconductor substrate and including a conductive film having a first side wall portion and a first bottom surface portion both of which are continuously formed on a first trench having a first width in a direction parallel to the principal surface, and a second conductor formed on the semiconductor substrate and including a conductive film having a second side wall portion and a second bottom surface portion both of which are continuously formed on a second trench having a second width in a direction parallel to the principal surface, the second width being larger than the first width.Type: ApplicationFiled: June 10, 2013Publication date: October 17, 2013Applicant: Elpida Memory, Inc.Inventors: Tsuyoshi Tomoyama, Keisuke Otsuka
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Publication number: 20100258907Abstract: An exemplary aspect of the invention provides a novel semiconductor device and a method for manufacturing the same.Type: ApplicationFiled: April 5, 2010Publication date: October 14, 2010Applicant: Elpida Memory, Inc.Inventors: Tsuyoshi Tomoyama, Keisuke Otsuka
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Patent number: 7667317Abstract: A semiconductor package comprises a substrate, which has two surfaces and comprises first and second electrical paths. On one of the surfaces, a semiconductor chip is mounted. The semiconductor chip comprises a plurality of pads, which include a first pad to be supplied with a power supply and a second pad to be grounded. On the other surface, at least one bypass capacitor is mounted. The bypass capacitor comprises first and second terminals, which are connected to the first and the second pads through the first and the second electrical paths, respectively.Type: GrantFiled: May 25, 2007Date of Patent: February 23, 2010Assignee: Elpida Memory, Inc.Inventors: Fumiyuki Osanai, Atsushi Hiraishi, Toshio Sugano, Tsuyoshi Tomoyama, Satoshi Isa, Masahiro Yamaguchi, Masanori Shibamoto
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Publication number: 20070273021Abstract: A semiconductor package comprises a substrate, which has two surfaces and comprises first and second electrical paths. On one of the surfaces, a semiconductor chip is mounted. The semiconductor chip comprises a plurality of pads, which include a first pad to be supplied with a power supply and a second pad to be grounded. On the other surface, at least one bypass capacitor is mounted. The bypass capacitor comprises first and second terminals, which are connected to the first and the second pads through the first and the second electrical paths, respectively.Type: ApplicationFiled: May 25, 2007Publication date: November 29, 2007Inventors: Fumiyuki Osanai, Atsushi Hiraishi, Toshio Sugano, Tsuyoshi Tomoyama, Satoshi Isa, Masahiro Yamaguchi, Masanori Shibamoto
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Publication number: 20070228580Abstract: A semiconductor device comprises a main circuit substrate and a plurality of sub-circuit substrates on which a semiconductor element mounted and which are stacked on the main circuit substrate so that mounting surfaces thereof face the main circuit substrate. Each of the sub-circuit substrates has a size larger than a size of the semiconductor element mounted thereon. The semiconductor device comprises a flip chip bonding portion formed between the sub-circuit substrate and the semiconductor element mounted thereon and further comprises adhesive material layers formed between the main circuit substrate and the semiconductor element of a first stage of the sub-circuit substrates and between the semiconductor element of a second or subsequent stage of the sub-circuit substrates and the sub-circuit substrate facing the semiconductor element of the second or subsequent stage of the sub-circuit substrates.Type: ApplicationFiled: March 29, 2007Publication date: October 4, 2007Applicant: ELPIDA MEMORY, INC.,Inventors: Masanori Shibamoto, Tsuyoshi Tomoyama