Abstract: A vehicle system includes a master ECU and a general ECU. The general ECU attaches a digital signature to transmission data including data (for example, a digest value of a program) and transmits the transmission data to the master ECU. The master ECU verifies the digital signature and the data and, when both the digital signature and the data are valid, determines that the general ECU is valid. The master ECU attaches a digital signature to transmission data including data of the master ECU and a session key and transmits the transmission data to the general ECU. The general ECU verifies the digital signature and the data and, when both the digital signature and the data are valid, the general ECU uses the session key included in the transmission data as a common key when performing subsequent communications.

Abstract: Disclosed is a system for detecting an attack, which includes a server and a plurality of vehicles capable of wirelessly communicating with each other. Each of the vehicles has a sensor, a sensor information acquisition unit, a traffic information reception unit, and a transmission unit that transmits the sensor information and the traffic information to the server. The server has a reception unit that receives the sensor information and the traffic information from the vehicles, a verification unit that verifies whether the sensor information and the traffic information are inconsistent with each other, and a notification unit that notifies, when the sensor information and the traffic information are inconsistent with each other, the vehicles of the inconsistency.

Abstract: Disclosed is a system for detecting an attack, which includes a server and a plurality of vehicles capable of wirelessly communicating with each other. Each of the vehicles has a sensor, a sensor information acquisition unit, a traffic information reception unit, and a transmission unit that transmits the sensor information and the traffic information to the server. The server has a reception unit that receives the sensor information and the traffic information from the vehicles, a verification unit that verifies whether the sensor information and the traffic information are inconsistent with each other, and a notification unit that notifies, when the sensor information and the traffic information are inconsistent with each other, the vehicles of the inconsistency.

Abstract: Provided is a vehicle system constituted by a master ECU and a general ECU. The general ECU attaches a digital signature to transmission data including the data (for example, a digest value of a program) and transmits the transmission data to the master ECU. The master ECU verifies the digital signature and the data and, when both the digital signature and the data are valid, determines that the general ECU is valid. The master ECU attaches a digital signature to transmission data including the data of the master ECU and a session key and transmits the transmission data to the general ECU. The general ECU verifies the digital signature and the data and, when both the digital signature and the data are valid, the general ECU uses the session key included in the transmission data as a common key when performing subsequent communications.

Abstract: Disclosed is a system for detecting an attack, which includes a server and a plurality of vehicles capable of wirelessly communicating with each other. Each of the vehicles has a sensor, a sensor information acquisition unit, a traffic information reception unit, and a transmission unit that transmits the sensor information and the traffic information to the server. The server has a reception unit that receives the sensor information and the traffic information from the vehicles, a verification unit that verifies whether the sensor information and the traffic information are inconsistent with each other, and a notification unit that notifies, when the sensor information and the traffic information are inconsistent with each other, the vehicles of the inconsistency.

Abstract: A light-emitting diode lighting apparatus includes a light source including plural grouped light-emitting diodes, plural lighting circuit parts to perform lighting control of the respective grouped light-emitting diodes of the light source individually, and a dimming control part that inputs a dimming signal from a dimming part and controls an output of each of the lighting circuit parts according to the dimming signal, and sequentially changes, when a dimming gradation is changed, outputs of the plural lighting circuit parts to new gradations in one period of the dimming signal.

Abstract: The input data comprising binary data to be stored are converted into multi-state data. A voltage of a level based on the converted multi-state data is applied to a source region to perform write operation to a memory transistor. As a result, the threshold voltage of the transistor is set to a value corresponding to the potential of the source region. In read operation a drain current generated in the memory transistor is detected and the multi-state data corresponding to the current are obtained. These multi-state data are converted into binary data to be outputted as output data.

Abstract: A semiconductor memory device having error checking/correcting functions includes a circuit (10) for generating a code for error checking/correcting based on information externally supplied and linking the information and the code to be transmitted to a memory cell array (1), and another circuit (11) for error checking and correcting read-out information from the information and the code which are read-out from the memory cell array so as to output correct read-out information. The code word generating circuit (10) and the error checking/correcting circuit (11) are formed of a masked ROM integrated on the same semiconductor chip (100) as that of the memory cell array (1) in the memory device.

Abstract: A semiconductor memory device having an error correcting circuit includes a circuit for generating a desired test signal with which memory cells used for error correction are to be tested, and another circuit for judging on an chip-basis whether memory cells of the semiconductor memory device are normal or not. The memory cells for error correction can be tested accurately by application of desired test signal. In addition, since there is no necessity of provision of a circuit for comparing externally applied data and data delivered from the semiconductor memory device, a test can be preformed readily.

Abstract: In a nonvolatile semiconductor device in which source metal interconnections for coupling to ground a source of a floating gate type memory transistor are commonly provided for each predetermined plurality of memory transistors, switching transistors are provided for each column for coupling to ground columns excluding the selected column when a single column is selected in response to an external column address. Each of the switching transistors operates in response to an inverted signal of an output of a column decoder. According to this structure, a variation in source potential of each memory transistor caused by the difference in source resistance associated with each of the memory transistors is reduced.

Abstract: A semiconductor memory device having an error checking and correcting (ECC) circuit is disclosed. This memory device includes data lines (10-21) from an ECC data generation circuit and bit lines (30-41) connected to the adjacent memory cells in a memory array (1), which are selectively connected at specified connecting portions (51, 52). When predetermined test data is inputted in order to detect undesired contact or interference between the memory cells, checker pattern data can be written in all the memory cells. Thus, despite the fact that the memory device includes an ECC circuit, a complete and easy memory cell checking is carried out.

Abstract: An EPROM as a nonvolatile semiconductor memory device includes a semiconductor substrate 1, a gate oxide layer 3 formed on the surface of the semiconductor substrate 1, a plurality of floating gates 4a and 4b formed on the gate oxide layer 3 so as to overlap one another at the portions 4ab thereof with a gate oxide layer 14 sandwiched between the overlapping portions 4ab, and control gate strips 5 formed on a gate oxide layer 6 which overlies the floating gates 4a and 4b.

Abstract: In a nonvolatile semiconductor device in which source metal interconnections for coupling to ground a source of a floating gate type memory transistor are commonly provided for each predetermined plurality of memory transistors, switching transistors are provided for each column for coupling to ground columns excluding the selected column when a single column is selected in response to an external column address. Each of the switching transistors operates in response to an inverted signal of an output of a column decoder. According to this structure, a variation in source potential of each memory transistor caused by the difference in source resistance associated with each of the memory transistors is reduced.

Abstract: In an output buffer circuit, two P channel MOSFET's (1, 2) are connected in parallel between a power supply terminal (16) and an output terminal (10), and two N channel MOSFET's (3, 4) are connected in parallel between the ground terminal (17) and the output terminal (10). When a normal power supply potential is applied to the power supply terminal (16), either one of the P channel MOSFET's (1, 2) or either one of N channel MOSFET's (3, 4) is turned on in response to an input signal. When a high potential is applied to the power supply terminal (16), two P channel MOSFET's (1, 2) or two N channel MOSFET's (3, 4) are turned on in response to the input signal.

Abstract: A memory cell array (100) of an EPROM includes a first data memory region (1a), a second data memory region (1b), a 2M code memory line (2a) and a 1M code memory line (2b). When both the first and the second data memory regions (1a, 1b) are normal, the EPROM may be used as a 2M bit EPROM, in which case a device code indicating that the EPROM is a 2M bit EPROM is read out from the 2M code memory line (2a). When a defective portion is present in one of the first and the second data memory regions (1a, 1b), the EPROM may be used as a 1M bit EPROM, in which case a device code indicating that the EPROM is a 1M bit EPROM is read out from the 1M code memory line (2b).

Abstract: A non-volatile memory cell includes a MOS transistor of double gate construction. The MOS memory transistor includes a floating gate structure which includes electrically separated first and second segmented floating gates (4a; 4b). For the purpose of writing data, electrons are independently injected into the first and second segmented floating gates. Data are stored in the MOS memory transistor in three different non-volatile storage levels; one with electron accumulated either one of the two segmented floating gates; another with electrons injected into both of the segmented floating gates; and still another with no electrons accumulated on both of the segmented floating gates.

Abstract: In an output buffer circuit, two P channel MOSFET's (1, 2) are connected in parallel between a power supply terminal (16) and an output terminal (10), and two N channel MOSFET's (3, 4) are connected in parallel between the ground terminal (17) and the output terminal (10). When a high potential is applied to the power supply terminal (16), either one of the P channel MOSFET's (1, 2) or either one of N channel MOSFET's (3, 4) is turned on in response to an input signal. When a normal power supply potential is applied to the power supply terminal (16), two P channel MOSFET's (1, 2) or two N channel MOSFET's (3, 4) are turned on in response to the input signal.

Abstract: An EEPROM having an ECC circuit further comprises a counter circuit. The ECC circuit checks and corrects bit errors included in data read out from a memory cell array. In addition, the ECC circuit generates a predetermined signal every time it corrects a bit error. The counter circuit counts a predetermined signal generated from the ECC circuit.

Abstract: Memory transistors are arranged in a plurality of rows and a plurality of columns. A source line is formed for every two bit lines formed in the column direction, each connected to the memory transistors of one column. A source region of each memory transistor is connected, on one side, to a source line adjacent thereto and, on the other side, to a source line through the source region of the adjacent memory transistor, through impurity regions respectively. A floating gate is formed to extend to a position under the corresponding source line. In another example, a source line is formed for each bit line formed in the column direction. The source region of each memory transistor is connected to the adjacent source lines on both sides thereof through impurity regions. The floating gate is formed to extend to positions under both adjacent source lines.

Abstract: A semiconductor memory device comprises a main memory 101 and a spare memory 102. When a part of the memory cells of the main memory 101 are defective, these defective memory cells are replaced by memory cells in the spare memory 102. The space memory 102 is decoded by the decoder circuit 104. The decoder circuit 104 is capable of decoding the spare memory 102 using a signal of an instruction memory 107. The instruction memory 107 is selectively enabled or disabled by an instruction control circuit 108. Consequently, in a state in which the instruction memory 107 is disabled by the control circuit 108, a spare memory selection signal is not provided from the instruction memory 107 to the decoder circuit 104 and the semiconductor memory device normally decodes the main memory including defective memory cells. As a result, the addresses and the like of the defective memory cells can be determined.