Patents by Inventor Tsuyoshi Tsunoda

Tsuyoshi Tsunoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240116759
    Abstract: Provided is a method for producing a positive electrode active material for an alkali ion secondary battery, the positive electrode active material containing a large amount of a transition metal and enabling operation of the battery. In the method for producing a positive electrode active material for an alkali ion secondary battery, in which the positive electrode active material contains 34 mol % or more of CrO+FeO+MnO+CoO+NiO, the method includes: a step of preparing a positive electrode active material precursor containing crystals; and a step of irradiating the positive electrode active material precursor with light to melt the crystals and amorphize at least a portion of the positive electrode active material precursor.
    Type: Application
    Filed: February 3, 2022
    Publication date: April 11, 2024
    Inventors: Tsuyoshi HONMA, Masafumi HIRATSUKA, Hideo YAMAUCHI, Ayumu TANAKA, Kei TSUNODA, Yoshinori YAMAZAKI
  • Patent number: 10672722
    Abstract: Disclosed is a wiring substrate including: a first wiring layer, a second wiring layer disposed on the first wiring layer interposed by an insulating film, and a via conductor passing through the insulating film in a thickness direction, the via conductor electrically connecting the first wiring layer and the second wiring layer. The second wiring layer and the via conductor include a second sintered metal layer and a first sintered metal layer arranged to surround the second sintered metal layer, and an average particle diameter of first metal particles forming the first sintered metal layer is smaller than an average particle diameter of second metal particles forming the second sintered metal layer.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: June 2, 2020
    Assignee: DAI NIPPON PRINTING Co., Ltd.
    Inventors: Ryohei Kasai, Tsuyoshi Tsunoda, Yuichi Yamamoto, Shuji Sagara, Masaya Tanaka
  • Publication number: 20190206808
    Abstract: Disclosed is a wiring substrate including: a first wiring layer, a second wiring layer disposed on the first wiring layer interposed by an insulating film, and a via conductor passing through the insulating film in a thickness direction, the via conductor electrically connecting the first wiring layer and the second wiring layer. The second wiring layer and the via conductor include a second sintered metal layer and a first sintered metal layer arranged to surround the second sintered metal layer, and an average particle diameter of first metal particles forming the first sintered metal layer is smaller than an average particle diameter of second metal particles forming the second sintered metal layer.
    Type: Application
    Filed: March 12, 2019
    Publication date: July 4, 2019
    Inventors: Ryohei Kasai, Tsuyoshi Tsunoda, Yuichi Yamamoto, Shuji Sagara, Masaya Tanaka
  • Patent number: 10276515
    Abstract: Disclosed is a wiring substrate including: a first wiring layer, a second wiring layer disposed on the first wiring layer interposed by an insulating film, and a via conductor passing through the insulating film in a thickness direction, the via conductor electrically connecting the first wiring layer and the second wiring layer. The second wiring layer and the via conductor include a second sintered metal layer and a first sintered metal layer arranged to surround the second sintered metal layer, and an average particle diameter of first metal particles forming the first sintered metal layer is smaller than an average particle diameter of second metal particles forming the second sintered metal layer.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: April 30, 2019
    Assignee: DAI NIPPON PRINTING Co., Ltd.
    Inventors: Ryohei Kasai, Tsuyoshi Tsunoda, Yuichi Yamamoto, Shuji Sagara, Masaya Tanaka
  • Publication number: 20180240760
    Abstract: Disclosed is a wiring substrate including: a first wiring layer, a second wiring layer disposed on the first wiring layer interposed by an insulating film, and a via conductor passing through the insulating film in a thickness direction, the via conductor electrically connecting the first wiring layer and the second wiring layer. The second wiring layer and the via conductor include a second sintered metal layer and a first sintered metal layer arranged to surround the second sintered metal layer, and an average particle diameter of first metal particles forming the first sintered metal layer is smaller than an average particle diameter of second metal particles forming the second sintered metal layer.
    Type: Application
    Filed: March 23, 2018
    Publication date: August 23, 2018
    Inventors: Ryohei KASAI, Tsuyoshi Tsunoda, Yuichi Yamamoto, Shuji Sagara, Masaya Tanaka
  • Patent number: 6703696
    Abstract: A semiconductor package is comprised of a semiconductor device 4 mounted on a die-pad 3, a wire 6 for electrically connecting some electrodes of the semiconductor device 4 and terminals 5 of lead frame, wires 8 for bonding the other electrodes of semiconductor device to the surface of die-pad for grounding, and molding compound 7 for encapsulating the outer area of semiconductor device 4 under a state where the back face of die-pad 3. The lower face and side face of terminals 5 are exposed, wherein portions plated with silver for connecting of wires on the surface of the die-pad are formed at points positioned between a peripheral edge of the die-pad and an outer edge of the semiconductor device while leaving spaces from both the edges. The adhesion of die-pad 3 to bonding compound 7 is improved to avoid the occurrence of wires coming-off even if heat is applied to the contact points of die-pad 3 to wires 8 when mounting semiconductor package on a printed circuit board.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: March 9, 2004
    Assignee: Dainippon Printing Co., Ltd.
    Inventors: Chikao Ikenaga, Kouji Tomita, Tsuyoshi Tsunoda
  • Publication number: 20020027297
    Abstract: A semiconductor package is comprised of a semiconductor device 4 mounted on a die-pad 3, a wire 6 for electrically connecting some electrodes of the semiconductor device 4 and terminals 5 of lead frame, wires 8 for bonding the other electrodes of semiconductor device to the surface of die-pad for grounding, molding compound 7 for encapsulating the outer area of semiconductor device 4 under a state where the back face of die-pad 3, the lower face and side face of terminals 5 are exposed, wherein portions for plated with silver connecting of wires on the surface of the die-pad are formed at points positioned between a peripheral edge of the die-pad and an outer edge of the semiconductor device with leaving spaces from both the edges. The adhesion of die-pad 3 to bonding compound 7 is improved so that no trouble of coming-off of wires occur even if heat is applied to the contact points of die-pad 3 to wires 8 when mounting semiconductor package on a printed circuit board.
    Type: Application
    Filed: August 31, 2001
    Publication date: March 7, 2002
    Inventors: Chikao Ikenaga, Kouji Tomita, Tsuyoshi Tsunoda