Patents by Inventor Tsuyoshi Yamano

Tsuyoshi Yamano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11947715
    Abstract: A control device according to an embodiment includes: a winding unit (30, 3001) that unwinds a wire having one end movably held by a user in a direction of the one end and winds the wire by an elastic force in a direction away from the one end, a wire lock unit (30, 3002) that locks unwinding of the wire from the winding unit, and a control unit (100) that controls an operation by the wire lock unit of locking the unwinding according to a relationship between a position of a virtual object disposed in a virtual space and a position, in the virtual space, corresponding to a position of the one end in a real space.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: April 2, 2024
    Assignee: SONY GROUP CORPORATION
    Inventors: Tsuyoshi Ishikawa, Takeshi Ogita, Yohei Fukuma, Taha Moriyama, Ikuo Yamano
  • Patent number: 5444282
    Abstract: A semiconductor device of a field effect transistor having an SOI structure is formed as below. Using a gate electrode 20 as a mask, n type impurities are implanted into an SOI layer of p type to form additional source/drain regions of intermediate concentration. Then, a relatively thin sidewall spacer is formed at the sidewall of the gate electrode. Using the sidewall spacer as a mask, a titanium silicide layer is formed in self-alignment on the surface of the SOI layer. Next, a relatively thick sidewall spacer is formed. Using this sidewall spacer as a mask, n type impurities are implanted to form a source/drain region of high concentration. According to this manufacturing step, over-etching of the source/drain region are prevented in performing anisotropic etching at the time of sidewall spacer formation.
    Type: Grant
    Filed: June 30, 1994
    Date of Patent: August 22, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuo Yamaguchi, Natsuo Ajika, Tsuyoshi Yamano
  • Patent number: 5416339
    Abstract: A semiconductor device for switching comprises a semiconductor substrate (10), three conductive regions (14, 16, 20) for providing a path for electrons to or from desired locations of the semiconductor substrate (10) formed at locations spaced apart on the surface of the semiconductor substrate (10, 28), a device (22, 24) for causing a current between the first and second conductive regions (14, 16), and a device (18) for forming electric field for diverting the caused current to the third conductive region (20). Since the current flowing to the first and second conductive regions (14, 16) is diverted to the third conductive region (20), switching operation between the first and second conductive regions (14, 16) is implemented.
    Type: Grant
    Filed: October 1, 1990
    Date of Patent: May 16, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masato Fujinaga, Norihiko Kotani, Tsuyoshi Yamano
  • Patent number: 5355012
    Abstract: A semiconductor device is an SOI type field effect transistor in which an active region is isolated and insulated by a transistor for isolation. A contact hole for isolation is formed in a gate dielectric thin film for isolation between a gate electrode of the transistor for isolation and a channel region below the gate electrode. In the semiconductor device thus structured, surplus carriers produced in a channel region below a transfer gate electrode are drawn through channel region and isolation contact hole into isolation gate electrode, thereby preventing such a disadvantageous phenomenon as a kink effect or the like due to a floating-substrate effect.
    Type: Grant
    Filed: April 28, 1993
    Date of Patent: October 11, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuo Yamaguchi, Natsuo Ajika, Tsuyoshi Yamano
  • Patent number: 5341028
    Abstract: A semiconductor device of a field effect transistor having an SOI structure is formed as below. Using a gate electrode 20 as a mask, n type impurities are implanted into an SOI layer of p type to form additional source/drain regions of intermediate concentration. Then, a relatively thin sidewall spacer is formed at the sidewall of the gate electrode. Using the sidewall spacer as a mask, a titanium silicide layer is formed in self-alignment on the surface of the SOI layer. Next, a relatively thick sidewall spacer is formed. Using this sidewall spacer as a mask, n type impurities are implanted to form a source/drain region of high concentration. According to this manufacturing step, over-etching of the source/drain region are prevented in performing anisotropic etching at the time of sidewall spacer formation.
    Type: Grant
    Filed: October 3, 1991
    Date of Patent: August 23, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuo Yamaguchi, Natsuo Ajika, Tsuyoshi Yamano
  • Patent number: 5060035
    Abstract: A field effect transistor comprises source, drain and channel regions in a semiconductor layer formed on an insulating substrate. An island-shaped semiconductor layer of a first conductivity type is formed on a major surface of the insulating substrate and isolated from the surroundings. Source and drain regions of a second conductivity type are formed spaced apart from each other in the island-shaped semiconductor layer so as to define the channel region having a part of a major surface of the island-shaped semiconductor layer as a channel surface. A gate electrode is formed on the channel surface through an insulating film. A sidewall insulating film is formed on a sidewall of other region than the source region in the island-shaped semiconductor layer. A semiconductor sidewall layer of the first conductivity type is formed on a sidewall of the island-shaped semiconductor layer corresponding to the source region and the sidewall insulating film.
    Type: Grant
    Filed: July 10, 1990
    Date of Patent: October 22, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tadashi Nishimura, Tsuyoshi Yamano