Abstract: A bulk acoustic wave (BAW) structure includes a single crystal piezoelectric material layer, a first electrode, a second electrode and an acoustic reflector. The first and second electrodes are respectively located on a first surface and a second surface of the single crystal piezoelectric material layer. The area of the second electrode is greater than or equal to that of the second surface of the single crystal piezoelectric material layer, and the contact area of the single crystal piezoelectric material layer with the second electrode is equal to the area of the second surface of the single crystal piezoelectric material layer. The acoustic reflector is disposed on a surface of the first electrode.

Abstract: A bulk acoustic wave (BAW) structure includes a single crystal piezoelectric material layer, a first electrode, a second electrode and an acoustic reflector. The first and second electrodes are respectively located on a first surface and a second surface of the single crystal piezoelectric material layer. The area of the second electrode is greater than or equal to that of the second surface of the single crystal piezoelectric material layer, and the contact area of the single crystal piezoelectric material layer with the second electrode is equal to the area of the second surface of the single crystal piezoelectric material layer. The acoustic reflector is disposed on a surface of the first electrode.

Abstract: A bulk acoustic wave (BAW) structure includes a single crystal piezoelectric material layer, a first electrode, a second electrode and an acoustic reflector. The first and second electrodes are respectively located on a first surface and a second surface of the single crystal piezoelectric material layer. The area of the second electrode is greater than or equal to that of the second surface of the single crystal piezoelectric material layer, and the contact area of the single crystal piezoelectric material layer with the second electrode is equal to the area of the second surface of the single crystal piezoelectric material layer. The acoustic reflector is disposed on a surface of the first electrode.

Abstract: A method for forming a connection structure is disclosed. A semiconductor structure having a first pad and a bump respectively on a bottom surface thereof is provided. A carrier having a second pad on a top surface thereof is provided. The second pad corresponds to the bump. An epoxy portion is disposed onto the second pad of the carrier. A diameter of the epoxy portion is less than or equal to a diameter of the bump. After depositing the epoxy portion, the bump is attached to the second pad via the epoxy portion.

Abstract: A method for forming a connection structure is disclosed. A semiconductor structure having a first pad and a bump respectively on a bottom surface thereof is provided. A carrier having a second pad on a top surface thereof is provided. The second pad corresponds to the bump. An epoxy portion is disposed onto the second pad of the carrier. A diameter of the epoxy portion is less than or equal to a diameter of the bump. After depositing the epoxy portion, the bump is attached to the second pad via the epoxy portion.

Abstract: A bulk acoustic wave (BAW) structure includes a single crystal piezoelectric material layer, a first electrode, a second electrode and an acoustic reflector. The first and second electrodes are respectively located on a first surface and a second surface of the single crystal piezoelectric material layer. The area of the second electrode is greater than or equal to that of the second surface of the single crystal piezoelectric material layer, and the contact area of the single crystal piezoelectric material layer with the second electrode is equal to the area of the second surface of the single crystal piezoelectric material layer. The acoustic reflector is disposed on a surface of the first electrode.

Abstract: A compound semiconductor device is provided, including a gallium arsenide (GaAs) substrate having a first protrusion portion and a second protrusion portion, wherein the first protrusion portion is formed over a first portion of the GaAs substrate and the second protrusion is formed over a second portion of the GaAs substrate. A first element is disposed over the first protrusion portion, and a second element is disposed over the second protrusion portion.

Abstract: A method of fabricating a microelectromechanical system (MEMS) device includes providing a semiconductor substrate having a semiconductor layer and an interconnect structure. A passivation layer and a photoresist layer are formed over the interconnect structure and a plurality of openings are formed in the photoresist layer to expose portions of the passivation layer. The passivation layer exposed by the openings and the interconnect structure thereunder are removed, forming a plurality of first trenches. The semiconductor layer exposed by the first trenches is removed, forming a plurality of second trenches in the semiconductor layer. An upper capping substrate is provided over the passivation layer, forming a first composite substrate. The semiconductor layer in the first composite substrate is thinned and portions of the thinned semiconductor layer are etched to form a third trench, wherein a suspended micromachined structure is formed in a region between the first, second and third trenches.

Abstract: A compound semiconductor device is provided, including a gallium arsenide (GaAs) substrate having a first protrusion portion and a second protrusion portion, wherein the first protrusion portion is formed over a first portion of the GaAs substrate and the second protrusion is formed over a second portion of the GaAs substrate. A first element is disposed over the first protrusion portion, and a second element is disposed over the second protrusion portion.

Abstract: A method of fabricating a microelectromechanical system (MEMS) device includes providing a semiconductor substrate having a semiconductor layer and an interconnect structure. A passivation layer and a photoresist layer are formed over the interconnect structure and a plurality of openings are formed in the photoresist layer to expose portions of the passivation layer. The passivation layer exposed by the openings and the interconnect structure thereunder are removed, forming a plurality of first trenches. The semiconductor layer exposed by the first trenches is removed, forming a plurality of second trenches in the semiconductor layer. An upper capping substrate is provided over the passivation layer, forming a first composite substrate. The semiconductor layer in the first composite substrate is thinned and portions of the thinned semiconductor layer are etched to form a third trench, wherein a suspended micromachined structure is formed in a region between the first, second and third trenches.

Abstract: A method and an apparatus for integrating a surface acoustic wave (SAW) filter and a transceiver are provided to solve the problem of having a large area of the prior-art integration of a SAW filter and a transceiver; wherein a device for integrating a SAW filter and a transceiver is provided and a component stack method is used to accomplish the integration of the SAW filter and the transceiver, and thus besides featuring a low cost and a small area as well as avoiding a signal loss, the invention can further include a design of encapsulating other components and chips, or even suitable to be used for various integrated circuit packaging technologies (such as QFP and BGA, etc.

Abstract: A low noise amplifier has the properties of low noise figure and high gain under a high-frequency operation. The low noise amplifier includes a first transistor, a first inductive impedance, a first gate voltage source, a matching circuit, an input, a second inductive impedance, a second transistor, a first capacitive impedance, a second gate voltage source, a third transistor, a third gate voltage source, a second capacitive impedance, a first impedance, a second impedance, a direct current source, a first output, a second output, a first resistor, a second resistor, a third resistor, a first bulk voltage source, a second bulk voltage source, and a third bulk voltage source.

Abstract: A structure having a shallow trench-deep trench isolation region for a semiconductor device is provided.

Abstract: A low noise amplifier has the properties of low noise figure and high gain under a high-frequency operation. The low noise amplifier includes a first transistor, a first inductive impedance, a first gate voltage source, a matching circuit, an input, a second inductive impedance, a second transistor, a first capacitive impedance, a second gate voltage source, a third transistor, a third gate voltage source, a second capacitive impedance, a first impedance, a second impedance, a direct current source, a first output, a second output, a first resistor, a second resistor, a third resistor, a first bulk voltage source, a second bulk voltage source, and a third bulk voltage source.

Abstract: A method of forming a shallow trench-deep trench isolation for a semiconductor device is provided.

Abstract: high-gain and low-noise low noise amplifier (LNA) includes a differential amplifier, a pre-amplifier and an impedance matching network. The differential amplifier includes a first input end and a second input end coupled to a grounded impedance. The pre-amplifier includes an input end and an output end. The impedance matching network is coupled between the first input end of the differential amplifier and the output end of the pre-amplifier for matching an input impedance of the differential amplifier with an output impedance of the pre-amplifier. The present invention provides a LNA structure with low noise, high gain and easy design.

Abstract: A single-ended input to differential output LNA with a cascode topology of the present invention overcomes a much greater consumption of current and area for the single-ended input to differential output LNA of the prior art. The LNA needs to supply an operating bias for each transistor. The LNA has a few transistors, a few capacitive impedances, and a few inductive impedances. The main objective of the present invention not only reduces costs and conserves area and current consumption, but also has a much higher linearity and gain under the same current consumption when compare to the prior art.

Abstract: A method and an apparatus for integrating a surface acoustic wave (SAW) filter and a transceiver are provided to solve the problem of having a large area of the prior-art integration of a SAW filter and a transceiver; wherein a device for integrating a SAW filter and a transceiver is provided and a component stack method is used to accomplish the integration of the SAW filter and the transceiver, and thus besides featuring a low cost and a small area as well as avoiding a signal loss, the invention can further include a design of encapsulating other components and chips, or even suitable to be used for various integrated circuit packaging technologies (such as QFP and BGA, etc.

Abstract: A single-ended input to differential output LNA with a cascode topology of the present invention overcomes a much greater consumption of current and area for the single-ended input to differential output LNA of the prior art. The LNA needs to supply an operating bias for each transistor. The LNA has a few transistors, a few capacitive impedances, and a few inductive impedances. The main objective of the present invention not only reduces costs and conserves area and current consumption, but also has a much higher linearity and gain under the same current consumption when compare to the prior art.

Abstract: A method and an apparatus for integrating a surface acoustic wave (SAW) filter and a transceiver are provided to solve the problem of having a large area of the prior-art integration of a SAW filter and a transceiver; wherein a device for integrating a SAW filter and a transceiver is provided and a component stack method is used to accomplish the integration of the SAW filter and the transceiver, and thus besides featuring a low cost and a small area as well as avoiding a signal loss, the invention can further include a design of encapsulating other components and chips, or even suitable to be used for various integrated circuit packaging technologies (such as QFP and BGA, etc.