Patents by Inventor Tsz-Hui Kuo

Tsz-Hui Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10504788
    Abstract: An inverter structure includes a first fin structure and a second fin structure respectively disposed within a P-type transistor region and an N-type transistor region on a substrate. Agate line is disposed on the substrate. A first end of the gate line is within the P-type transistor region, and a second end of the gate line is within the N-type transistor region. Two dummy gate lines are disposed at two sides of the gate line. Each dummy gate line has a third end within the P-type transistor region, and a fourth end within the N-type transistor region. A distance between the first end and the first fin structure is greater than a distance between the third end and the first fin structure. The distance between the second end and the second fin structure is smaller than a distance between the fourth end and the second fin structure.
    Type: Grant
    Filed: March 10, 2019
    Date of Patent: December 10, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Chi Lee, Han-Tsun Wang, Chang-Hung Chen, Po-Yu Yang, Mei-Ying Fan, Mu-Kai Tsai, Guan-Shyan Lin, Tsz-Hui Kuo, Cheng-Hsiung Chen
  • Publication number: 20190318964
    Abstract: An inverter structure includes a first fin structure and a second fin structure respectively disposed within a P-type transistor region and an N-type transistor region on a substrate. Agate line is disposed on the substrate. A first end of the gate line is within the P-type transistor region, and a second end of the gate line is within the N-type transistor region. Two dummy gate lines are disposed at two sides of the gate line. Each dummy gate line has a third end within the P-type transistor region, and a fourth end within the N-type transistor region. A distance between the first end and the first fin structure is greater than a distance between the third end and the first fin structure. The distance between the second end and the second fin structure is smaller than a distance between the fourth end and the second fin structure.
    Type: Application
    Filed: March 10, 2019
    Publication date: October 17, 2019
    Inventors: Wei-Chi Lee, Han-Tsun Wang, Chang-Hung Chen, Po-Yu Yang, Mei-Ying Fan, Mu-Kai Tsai, Guan-Shyan Lin, Tsz-Hui Kuo, Cheng-Hsiung Chen
  • Patent number: 10276446
    Abstract: An inverter structure includes a first fin structure and a second fin structure respectively disposed within a P-type transistor region and an N-type transistor region on a substrate. A gate line is disposed on the substrate. A first end of the gate line is within the P-type transistor region, and a second end of the gate line is within the N-type transistor region. Two dummy gate lines are disposed at two sides of the gate line. Each dummy gate line has a third end within the P-type transistor region, and a fourth end within the N-type transistor region. A distance between the first end and the first fin structure is greater than a distance between the third end and the first fin structure. The distance between the second end and the second fin structure is smaller than a distance between the fourth end and the second fin structure.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: April 30, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Chi Lee, Han-Tsun Wang, Chang-Hung Chen, Po-Yu Yang, Mei-Ying Fan, Mu-Kai Tsai, Guan-Shyan Lin, Tsz-Hui Kuo, Cheng-Hsiung Chen
  • Patent number: 7808248
    Abstract: A radio frequency test key structure includes a substrate, a bottom metal layer and a top metal layer. A narrow testing region is defined on the substrate. The bottom metal layer is positioned on the substrate and in the narrow testing region, and including an opening to expose parts of a device under test. The top metal layer is a metal pad in a sheet form, positioned in the narrow testing region and on the bottom metal layer. At least two signal pad regions and at least two ground pad regions are defined in the top metal layer. The signal pad regions and the ground pad regions are arranged in one row, and the row is parallel to the narrow testing region. Accordingly, the radio frequency test key structure can be positioned in a scribe line, and get an accurate testing result.
    Type: Grant
    Filed: October 5, 2006
    Date of Patent: October 5, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Yue-Shiun Lee, Cheng-Hsiung Chen, Tsz-Hui Kuo
  • Publication number: 20080083922
    Abstract: A radio frequency test key structure comprises a substrate, a bottom metal layer and a top metal layer. A narrow testing region is defined on the substrate. The bottom metal layer is positioned on the substrate and in the narrow testing region, and including an opening to expose parts of a device under test. The top metal layer is a metal pad in a sheet form, positioned in the narrow testing region and on the bottom metal layer. At least two signal pad regions and at least two ground pad regions are defined in the top metal layer. The signal pad regions and the ground pad regions are arranged in one row, and the row is parallel to the narrow testing region. Accordingly, the radio frequency test key structure can be positioned in a scribe line, and get an accurate testing result.
    Type: Application
    Filed: October 5, 2006
    Publication date: April 10, 2008
    Inventors: Yue-Shiun Lee, Cheng-Hsiung Chen, Tsz-Hui Kuo